Messages in this thread | | | From | Philipp Tomsich <> | Date | Wed, 13 Apr 2022 11:11:09 +0200 | Subject | Re: [PATCH v9 09/12] riscv: add RISC-V Svpbmt extension support |
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On Wed, 13 Apr 2022 at 05:03, Heiko Stuebner <heiko@sntech.de> wrote: > > Svpbmt (the S should be capitalized) is the > "Supervisor-mode: page-based memory types" extension > that specifies attributes for cacheability, idempotency > and ordering. > > The relevant settings are done in special bits in PTEs: > > Here is the svpbmt PTE format: > | 63 | 62-61 | 60-8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 > N MT RSW D A G U X W R V > ^ > > Of the Reserved bits [63:54] in a leaf PTE, the high bit is already > allocated (as the N bit), so bits [62:61] are used as the MT (aka > MemType) field. This field specifies one of three memory types that > are close equivalents (or equivalent in effect) to the three main x86 > and ARMv8 memory types - as shown in the following table. > > RISC-V > Encoding & > MemType RISC-V Description > ---------- ------------------------------------------------ > 00 - PMA Normal Cacheable, No change to implied PMA memory type > 01 - NC Non-cacheable, idempotent, weakly-ordered Main Memory > 10 - IO Non-cacheable, non-idempotent, strongly-ordered I/O memory > 11 - Rsvd Reserved for future standard use > > As the extension will not be present on all implementations, > implement a method to handle cpufeatures via alternatives > to not incur runtime penalties on cpu variants not supporting > specific extensions and patch relevant code parts at runtime. > > Co-developed-by: Wei Fu <wefu@redhat.com> > Signed-off-by: Wei Fu <wefu@redhat.com> > Co-developed-by: Liu Shaohua <liush@allwinnertech.com> > Signed-off-by: Liu Shaohua <liush@allwinnertech.com> > Co-developed-by: Guo Ren <guoren@kernel.org> > Signed-off-by: Guo Ren <guoren@kernel.org> > [moved to use the alternatives mechanism] > Signed-off-by: Heiko Stuebner <heiko@sntech.de> > Cc: Christoph Hellwig <hch@lst.de> > Cc: Arnd Bergmann <arnd@arndb.de> > Cc: Drew Fustini <drew@beagleboard.org> > Cc: Wei Fu <wefu@redhat.com> > Cc: Wei Wu <lazyparser@gmail.com> > Cc: Chen-Yu Tsai <wens@csie.org> > Cc: Maxime Ripard <maxime@cerno.tech> > Cc: Daniel Lustig <dlustig@nvidia.com> > Cc: Greg Favor <gfavor@ventanamicro.com> > Cc: Andrea Mondelli <andrea.mondelli@huawei.com> > Cc: Jonathan Behrens <behrensj@mit.edu> > Cc: Xinhaoqu (Freddie) <xinhaoqu@huawei.com> > Cc: Bill Huffman <huffman@cadence.com> > Cc: Nick Kossifidis <mick@ics.forth.gr> > Cc: Allen Baum <allen.baum@esperantotech.com> > Cc: Josh Scheid <jscheid@ventanamicro.com> > Cc: Richard Trauben <rtrauben@gmail.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
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