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    Subject[PATCH 5.16 230/285] perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids
    Date
    From: Kan Liang <kan.liang@linux.intel.com>

    commit e590928de7547454469693da9bc7ffd562e54b7e upstream.

    On Sapphire Rapids, the FRONTEND_RETIRED.MS_FLOWS event requires the
    FRONTEND MSR value 0x8. However, the current FRONTEND MSR mask doesn't
    support it.

    Update intel_spr_extra_regs[] to support it.

    Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
    Cc: stable@vger.kernel.org
    Link: https://lore.kernel.org/r/1648482543-14923-2-git-send-email-kan.liang@linux.intel.com
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/x86/events/intel/core.c | 2 +-
    1 file changed, 1 insertion(+), 1 deletion(-)

    --- a/arch/x86/events/intel/core.c
    +++ b/arch/x86/events/intel/core.c
    @@ -281,7 +281,7 @@ static struct extra_reg intel_spr_extra_
    INTEL_UEVENT_EXTRA_REG(0x012a, MSR_OFFCORE_RSP_0, 0x3fffffffffull, RSP_0),
    INTEL_UEVENT_EXTRA_REG(0x012b, MSR_OFFCORE_RSP_1, 0x3fffffffffull, RSP_1),
    INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
    - INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
    + INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff1f, FE),
    INTEL_UEVENT_EXTRA_REG(0x40ad, MSR_PEBS_FRONTEND, 0x7, FE),
    INTEL_UEVENT_EXTRA_REG(0x04c2, MSR_PEBS_FRONTEND, 0x8, FE),
    EVENT_EXTRA_END

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