Messages in this thread | | | Subject | Re: [PATCH v4,1/4] drm/mediatek: Adjust the timing of mipi signal from LP00 to LP11 | From | Rex-BC Chen <> | Date | Tue, 12 Apr 2022 15:37:48 +0800 |
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On Mon, 2022-04-11 at 10:31 +0800, xinlei.lee@mediatek.com wrote: > From: Jitao Shi <jitao.shi@mediatek.com> > > Old sequence: > 1. Pull the MIPI signal high > 2. Delay & Dsi_reset > 3. Set the dsi timing register > 4. dsi clk & lanes leave ulp mode and enter hs mode > > The sequence after patching is: > 1. Set the dsi timing register > 2. Pull the MIPI signal high > 3. Delay & Dsi_reset > 4. dsi clk & lanes leave ulp mode and enter hs mode > > Fixes: 2dd8075d2185 ("drm/mediatek: mtk_dsi: Use the drm_panel_bridge > API") > > Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> > Signed-off-by: Xinlei Lee <xinlei.lee@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c > b/drivers/gpu/drm/mediatek/mtk_dsi.c > index ccb0511b9cd5..262c027d8c2f 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -649,14 +649,14 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); > > - mtk_dsi_rxtx_control(dsi); > - usleep_range(30, 100); > - mtk_dsi_reset_dphy(dsi); > mtk_dsi_ps_control_vact(dsi); > mtk_dsi_set_vm_cmd(dsi); > mtk_dsi_config_vdo_timing(dsi); > mtk_dsi_set_interrupt_enable(dsi); > > + mtk_dsi_rxtx_control(dsi); > + usleep_range(30, 100); > + mtk_dsi_reset_dphy(dsi); > mtk_dsi_clk_ulp_mode_leave(dsi); > mtk_dsi_lane0_ulp_mode_leave(dsi); > mtk_dsi_clk_hs_mode(dsi, 0);
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
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