Messages in this thread | | | Date | Fri, 1 Apr 2022 10:33:39 -0700 | From | Dave Hansen <> | Subject | Re: [PATCHv7 21/30] x86/acpi, x86/boot: Add multiprocessor wake-up support |
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On 3/30/22 18:52, Kirill A. Shutemov wrote: > >>From ab320371f9ef8d24722394ec2505089e68737527 Mon Sep 17 00:00:00 2001 > From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> > Date: Thu, 15 Apr 2021 10:31:38 -0700 > Subject: [PATCH] x86/acpi, x86/boot: Add multiprocessor wake-up support > > Secondary CPU startup is currently performed with something called > the "INIT/SIPI protocol". This protocol requires assistance from > VMMs to boot guests. As should be a familiar story by now, that > support can not be provded to TDX guests because TDX VMMs are > not trusted by guests. > > To remedy this situation a new[1] "Multiprocessor Wakeup Structure" > has been added to to an existing ACPI table (MADT). This structure > provides the physical address of a "mailbox". A write to the mailbox > then steers the secondary CPU to the boot code. > > Add ACPI MADT wake structure parsing support and wake support. Use > this support to wake CPUs whenever it is present instead of INIT/SIPI. > > While this structure can theoretically be used on 32-bit kernels, > there are no 32-bit TDX guest kernels. It has not been tested and > can not practically *be* tested on 32-bit. Make it 64-bit only. > > 1. Details about the new structure can be found in ACPI v6.4, in the > "Multiprocessor Wakeup Structure" section. > > Co-developed-by: Sean Christopherson <sean.j.christopherson@intel.com> > Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com> > Reviewed-by: Andi Kleen <ak@linux.intel.com> > Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> > Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> > Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Looks good. I'm glad you were able to get rid of the extra-wakeup checks too.
Reviewed-by: Dave Hansen <dave.hansen@linux.intel.com>
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