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    Subject[PATCH 5.15 18/43] arm64: add ID_AA64ISAR2_EL1 sys register
    Date
    From: Joey Gouly <joey.gouly@arm.com>

    commit 9e45365f1469ef2b934f9d035975dbc9ad352116 upstream.

    This is a new ID register, introduced in 8.7.

    Signed-off-by: Joey Gouly <joey.gouly@arm.com>
    Cc: Will Deacon <will@kernel.org>
    Cc: Marc Zyngier <maz@kernel.org>
    Cc: James Morse <james.morse@arm.com>
    Cc: Alexandru Elisei <alexandru.elisei@arm.com>
    Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
    Cc: Reiji Watanabe <reijiw@google.com>
    Acked-by: Marc Zyngier <maz@kernel.org>
    Link: https://lore.kernel.org/r/20211210165432.8106-3-joey.gouly@arm.com
    Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
    ---
    arch/arm64/include/asm/cpu.h | 1 +
    arch/arm64/include/asm/sysreg.h | 15 +++++++++++++++
    arch/arm64/kernel/cpufeature.c | 9 +++++++++
    arch/arm64/kernel/cpuinfo.c | 1 +
    arch/arm64/kvm/sys_regs.c | 2 +-
    5 files changed, 27 insertions(+), 1 deletion(-)

    --- a/arch/arm64/include/asm/cpu.h
    +++ b/arch/arm64/include/asm/cpu.h
    @@ -51,6 +51,7 @@ struct cpuinfo_arm64 {
    u64 reg_id_aa64dfr1;
    u64 reg_id_aa64isar0;
    u64 reg_id_aa64isar1;
    + u64 reg_id_aa64isar2;
    u64 reg_id_aa64mmfr0;
    u64 reg_id_aa64mmfr1;
    u64 reg_id_aa64mmfr2;
    --- a/arch/arm64/include/asm/sysreg.h
    +++ b/arch/arm64/include/asm/sysreg.h
    @@ -180,6 +180,7 @@

    #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
    #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
    +#define SYS_ID_AA64ISAR2_EL1 sys_reg(3, 0, 0, 6, 2)

    #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
    #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
    @@ -764,6 +765,20 @@
    #define ID_AA64ISAR1_GPI_NI 0x0
    #define ID_AA64ISAR1_GPI_IMP_DEF 0x1

    +/* id_aa64isar2 */
    +#define ID_AA64ISAR2_RPRES_SHIFT 4
    +#define ID_AA64ISAR2_WFXT_SHIFT 0
    +
    +#define ID_AA64ISAR2_RPRES_8BIT 0x0
    +#define ID_AA64ISAR2_RPRES_12BIT 0x1
    +/*
    + * Value 0x1 has been removed from the architecture, and is
    + * reserved, but has not yet been removed from the ARM ARM
    + * as of ARM DDI 0487G.b.
    + */
    +#define ID_AA64ISAR2_WFXT_NI 0x0
    +#define ID_AA64ISAR2_WFXT_SUPPORTED 0x2
    +
    /* id_aa64pfr0 */
    #define ID_AA64PFR0_CSV3_SHIFT 60
    #define ID_AA64PFR0_CSV2_SHIFT 56
    --- a/arch/arm64/kernel/cpufeature.c
    +++ b/arch/arm64/kernel/cpufeature.c
    @@ -225,6 +225,10 @@ static const struct arm64_ftr_bits ftr_i
    ARM64_FTR_END,
    };

    +static const struct arm64_ftr_bits ftr_id_aa64isar2[] = {
    + ARM64_FTR_END,
    +};
    +
    static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
    ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
    ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
    @@ -637,6 +641,7 @@ static const struct __ftr_reg_entry {
    ARM64_FTR_REG(SYS_ID_AA64ISAR0_EL1, ftr_id_aa64isar0),
    ARM64_FTR_REG_OVERRIDE(SYS_ID_AA64ISAR1_EL1, ftr_id_aa64isar1,
    &id_aa64isar1_override),
    + ARM64_FTR_REG(SYS_ID_AA64ISAR2_EL1, ftr_id_aa64isar2),

    /* Op1 = 0, CRn = 0, CRm = 7 */
    ARM64_FTR_REG(SYS_ID_AA64MMFR0_EL1, ftr_id_aa64mmfr0),
    @@ -933,6 +938,7 @@ void __init init_cpu_features(struct cpu
    init_cpu_ftr_reg(SYS_ID_AA64DFR1_EL1, info->reg_id_aa64dfr1);
    init_cpu_ftr_reg(SYS_ID_AA64ISAR0_EL1, info->reg_id_aa64isar0);
    init_cpu_ftr_reg(SYS_ID_AA64ISAR1_EL1, info->reg_id_aa64isar1);
    + init_cpu_ftr_reg(SYS_ID_AA64ISAR2_EL1, info->reg_id_aa64isar2);
    init_cpu_ftr_reg(SYS_ID_AA64MMFR0_EL1, info->reg_id_aa64mmfr0);
    init_cpu_ftr_reg(SYS_ID_AA64MMFR1_EL1, info->reg_id_aa64mmfr1);
    init_cpu_ftr_reg(SYS_ID_AA64MMFR2_EL1, info->reg_id_aa64mmfr2);
    @@ -1151,6 +1157,8 @@ void update_cpu_features(int cpu,
    info->reg_id_aa64isar0, boot->reg_id_aa64isar0);
    taint |= check_update_ftr_reg(SYS_ID_AA64ISAR1_EL1, cpu,
    info->reg_id_aa64isar1, boot->reg_id_aa64isar1);
    + taint |= check_update_ftr_reg(SYS_ID_AA64ISAR2_EL1, cpu,
    + info->reg_id_aa64isar2, boot->reg_id_aa64isar2);

    /*
    * Differing PARange support is fine as long as all peripherals and
    @@ -1272,6 +1280,7 @@ u64 __read_sysreg_by_encoding(u32 sys_id
    read_sysreg_case(SYS_ID_AA64MMFR2_EL1);
    read_sysreg_case(SYS_ID_AA64ISAR0_EL1);
    read_sysreg_case(SYS_ID_AA64ISAR1_EL1);
    + read_sysreg_case(SYS_ID_AA64ISAR2_EL1);

    read_sysreg_case(SYS_CNTFRQ_EL0);
    read_sysreg_case(SYS_CTR_EL0);
    --- a/arch/arm64/kernel/cpuinfo.c
    +++ b/arch/arm64/kernel/cpuinfo.c
    @@ -391,6 +391,7 @@ static void __cpuinfo_store_cpu(struct c
    info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1);
    info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1);
    info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1);
    + info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1);
    info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
    info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1);
    info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1);
    --- a/arch/arm64/kvm/sys_regs.c
    +++ b/arch/arm64/kvm/sys_regs.c
    @@ -1518,7 +1518,7 @@ static const struct sys_reg_desc sys_reg
    /* CRm=6 */
    ID_SANITISED(ID_AA64ISAR0_EL1),
    ID_SANITISED(ID_AA64ISAR1_EL1),
    - ID_UNALLOCATED(6,2),
    + ID_SANITISED(ID_AA64ISAR2_EL1),
    ID_UNALLOCATED(6,3),
    ID_UNALLOCATED(6,4),
    ID_UNALLOCATED(6,5),

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