| Date | Thu, 31 Mar 2022 14:29:38 +0200 | From | Christoph Hellwig <> | Subject | Re: [PATCH v8 11/14] riscv: add RISC-V Svpbmt extension support |
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On Thu, Mar 24, 2022 at 01:07:07AM +0100, Heiko Stuebner wrote: > +asm(ALTERNATIVE("li %0, 0\t\nnop", "li %0, %1\t\nslli %0,%0,%2", 0, \ > + CPUFEATURE_SVPBMT, CONFIG_64BIT) \ > + : "=r"(_val) : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), "I"(ALT_SVPBMT_SHIFT))
This would be much more readable as;
asm(ALTERNATIVE("li %0, 0\t\nnop", "li %0, %1\t\nslli %0,%0,%2", 0, \ CPUFEATURE_SVPBMT, CONFIG_64BIT) \ : "=r"(_val) \ : "I"(prot##_SVPBMT >> ALT_SVPBMT_SHIFT), \ "I"(ALT_SVPBMT_SHIFT))
Otherwise this looks good to me:
Reviewed-by: Christoph Hellwig <hch@lst.de>
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