Messages in this thread | | | Date | Wed, 30 Mar 2022 15:43:25 +0200 | From | Peter Zijlstra <> | Subject | Re: [PATCH] x86/cpu: Add a third Alderlake CPU model number |
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On Thu, Mar 10, 2022 at 01:56:52PM -0800, Tony Luck wrote: > Existing suffix conventions only cover mobile/desktop/server options. > But this isn't any of those. Use "_N" as it matches the Intel naming > convention for this part. > > Signed-off-by: Tony Luck <tony.luck@intel.com> > --- > > Peter: What do you think about suffix proliferation? I tried to > get an answer about the target market segment for this CPU, but > didn't get an answer that is at all useful.
I'm not loving it, but seeing how they keep making these things into model numbers (instead of using a different differentiator), there's little we can do about it :-(
> arch/x86/include/asm/intel-family.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/x86/include/asm/intel-family.h b/arch/x86/include/asm/intel-family.h > index 048b6d5aff50..2f7b608f3e55 100644 > --- a/arch/x86/include/asm/intel-family.h > +++ b/arch/x86/include/asm/intel-family.h > @@ -107,6 +107,7 @@ > > #define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */ > #define INTEL_FAM6_ALDERLAKE_L 0x9A /* Golden Cove / Gracemont */ > +#define INTEL_FAM6_ALDERLAKE_N 0xBE
This is missing the /* Gracemont */ comment. That is, according to Google, Alder Lake N is an E core only SKU. So alternatively, we can call it: INTEL_FAM6_ATOM_GRACEMONT ....
/me runs like heck :-)
> #define INTEL_FAM6_RAPTORLAKE 0xB7
That too is missing the comment, but I can't actually find what it should be on wikichip so I suppose that's still sekrit or something.
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