Messages in this thread | | | Date | Sat, 26 Mar 2022 21:56:53 +0800 | From | Leo Yan <> | Subject | Re: [PATCH v4 2/4] perf arm-spe: Use SPE data source for neoverse cores |
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On Sat, Mar 26, 2022 at 10:52:01AM -0300, Arnaldo Carvalho de Melo wrote: > Em Sat, Mar 26, 2022 at 09:47:54PM +0800, Leo Yan escreveu: > > Hi Ali, German, > > > > On Thu, Mar 24, 2022 at 06:33:21PM +0000, Ali Saidi wrote: > > > > [...] > > > > > +static void arm_spe__synth_data_source_neoverse(const struct arm_spe_record *record, > > > + union perf_mem_data_src *data_src) > > > { > > > - union perf_mem_data_src data_src = { 0 }; > > > + /* > > > + * Even though four levels of cache hierarchy are possible, no known > > > + * production Neoverse systems currently include more than three levels > > > + * so for the time being we assume three exist. If a production system > > > + * is built with four the this function would have to be changed to > > > + * detect the number of levels for reporting. > > > + */ > > > > > > - if (record->op == ARM_SPE_LD) > > > - data_src.mem_op = PERF_MEM_OP_LOAD; > > > - else > > > - data_src.mem_op = PERF_MEM_OP_STORE; > > > > Firstly, apologize that I didn't give clear idea when Ali sent patch sets > > v2 and v3. > > Ok, removing this as well. > > Thanks for reviewing.
Thanks a lot, Arnaldo. Yeah, it's good to give a bit more time to dismiss the concerns in this patch.
Sorry again for the inconvenience.
Leo
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