Messages in this thread | | | From | Atish Patra <> | Date | Wed, 23 Mar 2022 09:34:22 -0700 | Subject | Re: [PATCH] RISC-V: Enable perf events by default |
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On Wed, Mar 23, 2022 at 2:00 AM Anup Patel <apatel@ventanamicro.com> wrote: > > Let us enable perf events by default in RV32 and RV64 defconfigs > so that we can use RISC-V PMU drivers on various RISC-V platforms. > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > --- > arch/riscv/configs/defconfig | 1 + > arch/riscv/configs/rv32_defconfig | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig > index f120fcc43d0a..57aaedc7cf74 100644 > --- a/arch/riscv/configs/defconfig > +++ b/arch/riscv/configs/defconfig > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y > CONFIG_BLK_DEV_INITRD=y > CONFIG_EXPERT=y > # CONFIG_SYSFS_SYSCALL is not set > +CONFIG_PERF_EVENTS=y > CONFIG_SOC_MICROCHIP_POLARFIRE=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig > index 8b56a7f1eb06..21d422e740d5 100644 > --- a/arch/riscv/configs/rv32_defconfig > +++ b/arch/riscv/configs/rv32_defconfig > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y > CONFIG_BLK_DEV_INITRD=y > CONFIG_EXPERT=y > # CONFIG_SYSFS_SYSCALL is not set > +CONFIG_PERF_EVENTS=y > CONFIG_SOC_SIFIVE=y > CONFIG_SOC_VIRT=y > CONFIG_ARCH_RV32I=y > -- > 2.25.1 >
I think it is better to enable perf events by adding CONFIG_PROFILING to the defconfig similar to other ISAs.
-- Regards, Atish
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