Messages in this thread Patch in this message | | | From | Dongli Si <> | Subject | [PATCH v4] perf/x86/amd: Don't touch the Host-only bit inside the guest hypervisor | Date | Sun, 20 Mar 2022 08:21:06 +0800 |
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From: Dongli Si <sidongli1997@gmail.com>
With nested virtualization on AMD Milan, if "perf record" is run in an L1 hypervisor with an L2 guest, the following warning is emitted in the L1 guest.
[] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write 0x0000020000510076) at rIP: 0xffffffff81003a50 (x86_pmu_enable_all+0x60/0x100) [] Call Trace: [] <IRQ> [] ? x86_pmu_enable+0x146/0x300 [] __perf_install_in_context+0x150/0x170
The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host (L0), while the L1 hypervisor Performance Monitor Unit should avoid such use.
Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled") Signed-off-by: Dongli Si <sidongli1997@gmail.com> Tested-by: Liam Merwick <liam.merwick@oracle.com> Reviewed-by: Liam Merwick <liam.merwick@oracle.com> --- v4: Remove my run_as_host function for better descriptive. v3: https://lore.kernel.org/all/20220314042254.1487836-1-sidongli1997@gmail.com/ v2: https://lore.kernel.org/all/20220310183404.1291725-1-sidongli1997@gmail.com/ v1: https://lore.kernel.org/all/20220227132640.3-1-sidongli1997@gmail.com/
arch/x86/events/amd/core.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/x86/events/amd/core.c b/arch/x86/events/amd/core.c index 9687a8aef01c..3fafd1e46ada 100644 --- a/arch/x86/events/amd/core.c +++ b/arch/x86/events/amd/core.c @@ -8,6 +8,7 @@ #include <linux/jiffies.h> #include <asm/apicdef.h> #include <asm/nmi.h> +#include <asm/hypervisor.h> #include "../perf_event.h" @@ -1027,7 +1028,8 @@ void amd_pmu_enable_virt(void) { struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events); - cpuc->perf_ctr_virt_mask = 0; + if (hypervisor_is_type(X86_HYPER_NATIVE)) + cpuc->perf_ctr_virt_mask = 0; /* Reload all events */ amd_pmu_disable_all(); -- 2.32.0
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