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    Subject[PATCH v4 3/3] arm64: dts: qcom: sc7280: add lpass lpi pin controller node
    Date
    Add LPASS LPI pinctrl node required for Audio functionality on sc7280
    based platforms.

    Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com>
    Co-developed-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
    Signed-off-by: Venkata Prasad Potturu <quic_potturu@quicinc.com>
    ---
    arch/arm64/boot/dts/qcom/sc7280.dtsi | 147 +++++++++++++++++++++++++++++++++++
    1 file changed, 147 insertions(+)

    diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
    index acea8ab..5fd0aad 100644
    --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
    @@ -1987,6 +1987,153 @@
    qcom,bcm-voters = <&apps_bcm_voter>;
    };

    + lpass_tlmm: pinctrl@33c0000 {
    + compatible = "qcom,sc7280-lpass-lpi-pinctrl";
    + reg = <0 0x33c0000 0x0 0x20000>,
    + <0 0x3550000 0x0 0x10000>;
    + gpio-controller;
    + #gpio-cells = <2>;
    + gpio-ranges = <&lpass_tlmm 0 0 15>;
    +
    + #clock-cells = <1>;
    +
    + dmic01_active: dmic01-active {
    + clk {
    + pins = "gpio6";
    + function = "dmic1_clk";
    + drive-strength = <8>;
    + output-high;
    + };
    +
    + data {
    + pins = "gpio7";
    + function = "dmic1_data";
    + drive-strength = <8>;
    + };
    + };
    +
    + dmic01_sleep: dmic01-sleep {
    + clk {
    + pins = "gpio6";
    + function = "dmic1_clk";
    + drive-strength = <2>;
    + bias-disable;
    + output-low;
    + };
    +
    + data {
    + pins = "gpio7";
    + function = "dmic1_data";
    + drive-strength = <2>;
    + pull-down;
    + };
    + };
    +
    + dmic23_active: dmic02-active {
    + clk {
    + pins = "gpio8";
    + function = "dmic2_clk";
    + drive-strength = <8>;
    + output-high;
    + };
    +
    + data {
    + pins = "gpio9";
    + function = "dmic2_data";
    + drive-strength = <8>;
    + };
    + };
    +
    + dmic23_sleep: dmic02-sleep {
    + clk {
    + pins = "gpio8";
    + function = "dmic2_clk";
    + drive-strength = <2>;
    + bias-disable;
    + output-low;
    + };
    +
    + data {
    + pins = "gpio9";
    + function = "dmic2_data";
    + drive-strength = <2>;
    + pull-down;
    + };
    + };
    +
    + rx_swr_active: rx-swr-active {
    + clk {
    + pins = "gpio3";
    + function = "swr_rx_clk";
    + drive-strength = <2>;
    + slew-rate = <1>;
    + bias-disable;
    + };
    +
    + data {
    + pins = "gpio4", "gpio5";
    + function = "swr_rx_data";
    + drive-strength = <2>;
    + slew-rate = <1>;
    + bias-bus-hold;
    + };
    + };
    +
    + rx_swr_sleep: rx-swr-sleep {
    + clk {
    + pins = "gpio3";
    + function = "swr_rx_clk";
    + drive-strength = <2>;
    + input-enable;
    + bias-pull-down;
    + };
    +
    + data {
    + pins = "gpio4", "gpio5";
    + function = "swr_rx_data";
    + drive-strength = <2>;
    + input-enable;
    + bias-pull-down;
    + };
    + };
    +
    + tx_swr_active: tx-swr-active {
    + clk {
    + pins = "gpio0";
    + function = "swr_tx_clk";
    + drive-strength = <2>;
    + slew-rate = <1>;
    + bias-disable;
    + };
    +
    + data {
    + pins = "gpio1", "gpio2", "gpio14";
    + function = "swr_tx_data";
    + drive-strength = <2>;
    + slew-rate = <1>;
    + bias-bus-hold;
    + };
    + };
    +
    + tx_swr_sleep: tx-swr-sleep {
    + clk {
    + pins = "gpio0";
    + function = "swr_tx_clk";
    + drive-strength = <2>;
    + input-enable;
    + bias-pull-down;
    + };
    +
    + data {
    + pins = "gpio1", "gpio2", "gpio14";
    + function = "swr_tx_data";
    + drive-strength = <2>;
    + input-enable;
    + bias-bus-hold;
    + };
    + };
    + };
    +
    gpu: gpu@3d00000 {
    compatible = "qcom,adreno-635.0", "qcom,adreno";
    reg = <0 0x03d00000 0 0x40000>,
    --
    2.7.4
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