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    Subject[PATCH 5.15 08/25] arm64: dts: agilex: use the compatible "intel,socfpga-agilex-hsotg"
    Date
    From: Dinh Nguyen <dinguyen@kernel.org>

    [ Upstream commit 268a491aebc25e6dc7c618903b09ac3a2e8af530 ]

    The DWC2 USB controller on the Agilex platform does not support clock
    gating, so use the chip specific "intel,socfpga-agilex-hsotg"
    compatible.

    Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
    Signed-off-by: Sasha Levin <sashal@kernel.org>
    ---
    arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++--
    1 file changed, 2 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
    index 163f33b46e4f..de1e98c99ec5 100644
    --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
    +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
    @@ -502,7 +502,7 @@
    };

    usb0: usb@ffb00000 {
    - compatible = "snps,dwc2";
    + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
    reg = <0xffb00000 0x40000>;
    interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
    phys = <&usbphy0>;
    @@ -515,7 +515,7 @@
    };

    usb1: usb@ffb40000 {
    - compatible = "snps,dwc2";
    + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2";
    reg = <0xffb40000 0x40000>;
    interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
    phys = <&usbphy0>;
    --
    2.34.1


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