Messages in this thread | | | Date | Thu, 17 Mar 2022 12:25:47 +0100 | From | Peter Zijlstra <> | Subject | Re: [PATCH 2/7] x86/msr: Add PerfCntrGlobal* registers |
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On Thu, Mar 17, 2022 at 11:58:31AM +0530, Sandipan Das wrote: > Add MSR definitions that will be used to enable the new AMD > Performance Monitoring Version 2 (PerfMonV2) features. These > include: > > * Performance Counter Global Control (PerfCntrGlobalCtl) > * Performance Counter Global Status (PerfCntrGlobalStatus) > * Performance Counter Global Status Clear (PerfCntrGlobalStatusClr) > > The new Performance Counter Global Control and Status MSRs > provide an interface for enabling or disabling multiple > counters at the same time and for testing overflow without > probing the individual registers for each PMC. > > The availability of these registers is indicated through the > PerfMonV2 feature bit of CPUID Fn80000022[EAX]. > > Signed-off-by: Sandipan Das <sandipan.das@amd.com> > --- > arch/x86/include/asm/msr-index.h | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index a4a39c3e0f19..61d1a55e15b8 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -504,6 +504,11 @@ > #define AMD_CPPC_DES_PERF(x) (((x) & 0xff) << 16) > #define AMD_CPPC_ENERGY_PERF_PREF(x) (((x) & 0xff) << 24) > > +/* AMD Performance Counter Global Status and Control MSRs */ > +#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS 0xc0000300 > +#define MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR 0xc0000302 > +#define MSR_AMD64_PERF_CNTR_GLOBAL_CTL 0xc0000301
My OCD would suggest ordering them by number :-)
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