Messages in this thread | | | Subject | Re: [PATCH v6 1/6] RISC-V: Correctly print supported extensions | From | Joe Perches <> | Date | Thu, 17 Mar 2022 20:41:08 -0700 |
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On Mon, 2022-03-14 at 13:38 -0700, Atish Patra wrote: > From: Tsukasa OI <research_trasio@irq.a4lg.com> > > This commit replaces BITS_PER_LONG with number of alphabet letters. [] > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c [] > @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) > } > > memset(print_str, 0, sizeof(print_str)); > - for (i = 0, j = 0; i < BITS_PER_LONG; i++) > + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) > if (riscv_isa[0] & BIT_MASK(i)) > print_str[j++] = (char)('a' + i);
probably better to add braces for the for loops too
> pr_info("riscv: ISA extensions %s\n", print_str); > > memset(print_str, 0, sizeof(print_str)); > - for (i = 0, j = 0; i < BITS_PER_LONG; i++) > + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) > if (elf_hwcap & BIT_MASK(i)) > print_str[j++] = (char)('a' + i); > pr_info("riscv: ELF capabilities %s\n", print_str);
and here.
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