Messages in this thread | | | Date | Wed, 16 Mar 2022 18:11:53 -0700 | Subject | Re: [Intel-gfx] [PATCH v11 1/5] drm/i915/gsc: add gsc as a mei auxiliary device | From | "Ceraolo Spurio, Daniele" <> |
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<snip>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index ddbc7a685a50..63c56d668963 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -976,6 +976,8 @@ > #define GEN12_COMPUTE2_RING_BASE 0x1e000 > #define GEN12_COMPUTE3_RING_BASE 0x26000 > #define BLT_RING_BASE 0x22000 > +#define DG1_GSC_HECI1_BASE 0x00258000 > +#define DG1_GSC_HECI2_BASE 0x00259000
You ended up keeping the HECI1 define. Not a blocker, so:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
> > > > diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h > index f9b955810593..576d15a04c9e 100644 > --- a/drivers/gpu/drm/i915/intel_device_info.h > +++ b/drivers/gpu/drm/i915/intel_device_info.h > @@ -141,6 +141,8 @@ enum intel_ppgtt_type { > func(has_flat_ccs); \ > func(has_global_mocs); \ > func(has_gt_uc); \ > + func(has_heci_pxp); \ > + func(has_heci_gscfi); \ > func(has_guc_deprivilege); \ > func(has_l3_dpf); \ > func(has_llc); \ > diff --git a/include/linux/mei_aux.h b/include/linux/mei_aux.h > new file mode 100644 > index 000000000000..587f25128848 > --- /dev/null > +++ b/include/linux/mei_aux.h > @@ -0,0 +1,19 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > +/* > + * Copyright (c) 2022, Intel Corporation. All rights reserved. > + */ > +#ifndef _LINUX_MEI_AUX_H > +#define _LINUX_MEI_AUX_H > + > +#include <linux/auxiliary_bus.h> > + > +struct mei_aux_device { > + struct auxiliary_device aux_dev; > + int irq; > + struct resource bar; > +}; > + > +#define auxiliary_dev_to_mei_aux_dev(auxiliary_dev) \ > + container_of(auxiliary_dev, struct mei_aux_device, aux_dev) > + > +#endif /* _LINUX_MEI_AUX_H */
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