Messages in this thread | | | Date | Mon, 14 Mar 2022 14:33:53 +0800 | From | Leo Yan <> | Subject | Re: [PATCH v2 2/2] perf mem: Support HITM for when mem_lvl_num is used |
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On Sun, Mar 13, 2022 at 07:19:33PM +0000, Ali Saidi wrote:
[...]
> > > > + if (lvl & P(LVL, L3) || lnum == P(LVLNUM, L4)) { > > > > > > According to a comment in the previous patch, using L4 is specific to Neoverse, right? > > > > > > Maybe we need to distinguish the Neoverse case from the generic one here as well > > > > > > if (is_neoverse) > > > // treat L4 as llc > > > else > > > // treat L3 as llc > > > > I personally think it's not good idea to distinguish platforms in the decoding code. > > I agree here. The more we talk about this, the more I'm wondering if we're > spending too much code solving a problem that doesn't exist. I know of no > Neoverse systems that actually have 4 cache levels, they all actually have three > even though it's technically possible to have four. I have some doubts anyone > will actually build four levels of cache and perhaps the most prudent path here > is to assume only three levels (and adjust the previous patch) until someone > actually produces a system with four levels instead of a lot of code that is > never actually exercised?
I am not right person to say L4 cache is not implemented in Neoverse platforms; my guess for a "System cache" data source might be L3 or L4 and it is a implementation dependent. Maybe German or Arm mates could confirm for this.
Thanks, Leo
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