Messages in this thread | | | From | Dongli Si <> | Subject | Re: [PATCH v2] perf/x86/amd: Don't touch the Host-only bit inside the guest hypervisor | Date | Mon, 14 Mar 2022 12:19:30 +0800 |
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On 11/03/2022 22:25, Liam Merwick wrote: > On 10/03/2022 18:34, Dongli Si wrote: > > From: Dongli Si <sidongli1997@gmail.com> > > > > With nested virtualization, when the guest hypervisor runs a nested guest > > and if uses "perf record" in an AMD Milan guest hypervisor, the guest > > hypervisor dmesg will reports the following warning message: > > I think it might be clearer with L0/L1/L2 terminology. Maybe something > like the following? > > "With nested virtualization on AMD Milan, if "perf record" is run in an > L1 hypervisor with an L2 guest, the following warning is emitted in > the L1 guest." > > > > > > [] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write 0x0000020000510076) > > at rIP: 0xffffffff81003a50 (x86_pmu_enable_all+0x60/0x100) > > [] Call Trace: > > [] <IRQ> > > [] ? x86_pmu_enable+0x146/0x300 > > [] __perf_install_in_context+0x150/0x170 > > > > The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host, while > > the guest hypervisor performance monitor unit should avoid such use. > > "The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host (L0), > while the L1 hypervisor Performance Monitor Unit should avoid such use." > > > > > > > Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled") > > Signed-off-by: Dongli Si <sidongli1997@gmail.com> > > Tested-by: Liam Merwick <liam.merwick@oracle.com> > Reviewed-by: Liam Merwick <liam.merwick@oracle.com>
Hi Liam, I will improve the description based on your suggestion and resend the patch, thanks!
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