Messages in this thread | | | From | Medad Young <> | Date | Mon, 14 Mar 2022 13:22:15 +0800 | Subject | Re: [PATCH v3 1/3] ARM: dts: nuvoton: Add new device node |
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OK, I will check it. thanks for your comment
B.R. Medad
Jonathan Neuschäfer <j.neuschaefer@gmx.net> 於 2022年3月12日 週六 上午10:31寫道: > > >Subject: [PATCH v3 1/3] ARM: dts: nuvoton: Add new device node > > To make it more obvious what this patch is about, I suggest something like: > > [PATCH v3 1/3] ARM: dts: nuvoton: Add memory controller node > > > This arguably makes the next line in the commit message redundant, > but there is other useful information that can be added there, if you > like, such as how the kernel is going to use the memory controller. > > > Best regards, > Jonathan > > On Fri, Mar 11, 2022 at 09:42:43AM +0800, Medad CChien wrote: > > Add NPCM memory controller device node > > > > Signed-off-by: Medad CChien <ctcchien@nuvoton.com> > > --- > > arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi > > index 3696980a3da1..ba542b26941e 100644 > > --- a/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi > > +++ b/arch/arm/boot/dts/nuvoton-common-npcm7xx.dtsi > > @@ -106,6 +106,13 @@ > > interrupt-parent = <&gic>; > > ranges; > > > > + mc: memory-controller@f0824000 { > > + compatible = "nuvoton,npcm750-memory-controller"; > > + reg = <0x0 0xf0824000 0x0 0x1000>; > > + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; > > + status = "disabled"; > > + }; > > + > > rstc: rstc@f0801000 { > > compatible = "nuvoton,npcm750-reset"; > > reg = <0xf0801000 0x70>; > > -- > > 2.17.1 > >
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