Messages in this thread | | | Date | Thu, 3 Feb 2022 12:10:13 +0000 | Subject | Re: [PATCH 1/1] coresight: no-op refactor to make INSTP0 check more idiomatic | From | Suzuki K Poulose <> |
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On 03/02/2022 11:53, James Clark wrote: > The spec says this: > > P0 tracing support field. The permitted values are: > 0b00 Tracing of load and store instructions as P0 elements is not > supported. > 0b11 Tracing of load and store instructions as P0 elements is > supported, so TRCCONFIGR.INSTP0 is supported. > > All other values are reserved. > > The value we are looking for is 0b11 so simplify this. The double read > and && was a bit obfuscated. > > Suggested-by: Suzuki Poulose <suzuki.poulose@arm.com> > Signed-off-by: James Clark <james.clark@arm.com>
Thanks, Queued.
Cheers Suzuki
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