Messages in this thread | | | Date | Mon, 28 Feb 2022 10:32:57 +0100 | Subject | Re: [PATCH v3 3/3] arm64: dts: rockchip: Add sata nodes to rk356x | From | Johan Jonker <> |
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Hi Frank,
On 2/27/22 19:28, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > RK356x supports up to 3 sata controllers which were compatible with the > existing snps,dwc-ahci binding. > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > --- > changes in v3: > - fix combphy error by moving sata0 to rk3568.dtsi > - remove clock-names and interrupt-names > changes in v2: > - added sata0 + 1, but have only tested sata2 > --- > arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 +++++++++++++ > arch/arm64/boot/dts/rockchip/rk356x.dtsi | 26 ++++++++++++++++++++++++ > 2 files changed, 40 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > index 5b0f528d6818..2a2f65899d47 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi > @@ -8,6 +8,19 @@ > / { > compatible = "rockchip,rk3568"; > > + sata0: sata@fc000000 {
> + compatible = "snps,dwc-ahci";
compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
Compatible strings must be SoC orientated. By using a fall back string the driver doesn't have to be changed for every new SoC. Add binding in extra patch.
> + reg = <0 0xfc000000 0 0x1000>; > + clocks = <&cru ACLK_SATA0>, <&cru CLK_SATA0_PMALIVE>, > + <&cru CLK_SATA0_RXOOB>; > + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&combphy0 PHY_TYPE_SATA>; > + phy-names = "sata-phy"; > + ports-implemented = <0x1>; > + power-domains = <&power RK3568_PD_PIPE>; > + status = "disabled"; > + }; > + > pipe_phy_grf0: syscon@fdc70000 { > compatible = "rockchip,rk3568-pipe-phy-grf", "syscon"; > reg = <0x0 0xfdc70000 0x0 0x1000>; > @@ -114,3 +127,4 @@ power-domain@RK3568_PD_PIPE { > #power-domain-cells = <0>; > }; > }; > + > diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > index 7cdef800cb3c..484c5ace718a 100644 > --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi > @@ -230,6 +230,32 @@ scmi_shmem: sram@0 { > }; > }; > > + sata1: sata@fc400000 {
> + compatible = "snps,dwc-ahci";
dito
> + reg = <0 0xfc400000 0 0x1000>; > + clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>, > + <&cru CLK_SATA1_RXOOB>; > + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&combphy1 PHY_TYPE_SATA>; > + phy-names = "sata-phy"; > + ports-implemented = <0x1>; > + power-domains = <&power RK3568_PD_PIPE>; > + status = "disabled"; > + }; > + > + sata2: sata@fc800000 {
> + compatible = "snps,dwc-ahci";
dito
> + reg = <0 0xfc800000 0 0x1000>; > + clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>, > + <&cru CLK_SATA2_RXOOB>; > + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; > + phys = <&combphy2 PHY_TYPE_SATA>; > + phy-names = "sata-phy"; > + ports-implemented = <0x1>; > + power-domains = <&power RK3568_PD_PIPE>; > + status = "disabled"; > + }; > + > gic: interrupt-controller@fd400000 { > compatible = "arm,gic-v3"; > reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
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