Messages in this thread | | | Date | Thu, 24 Feb 2022 09:29:55 +0100 | From | Gabriel Paubert <> | Subject | Re: [PATCH] powerpc/32: Clear volatile regs on syscall exit |
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On Wed, Feb 23, 2022 at 05:27:39PM -0600, Segher Boessenkool wrote: > On Wed, Feb 23, 2022 at 09:48:09PM +0100, Gabriel Paubert wrote: > > On Wed, Feb 23, 2022 at 06:11:36PM +0100, Christophe Leroy wrote: > > > + /* Zero volatile regs that may contain sensitive kernel data */ > > > + li r0,0 > > > + li r4,0 > > > + li r5,0 > > > + li r6,0 > > > + li r7,0 > > > + li r8,0 > > > + li r9,0 > > > + li r10,0 > > > + li r11,0 > > > + li r12,0 > > > + mtctr r0 > > > + mtxer r0 > > > > Here, I'm almost sure that on some processors, it would be better to > > separate mtctr form mtxer. mtxer is typically very expensive (pipeline > > flush) but I don't know what's the best ordering for the average core. > > mtxer is cheaper than mtctr on many cores :-)
We're speaking of 32 bit here I believe; on my (admittedly old) paper copy of PowerPC 604 user's manual, I read in a footnote:
"The mtspr (XER) instruction causes instructions to be flushed when it executes."
Also a paragraph about "PostDispatch Serialization Mode" which reads: "All instructions following the postdispatch serialization instruction are flushed, refetched, and reexecuted."
Then it goes on to list the affected instructions which starts with: mtsper(xer), mcrxr, isync, ...
I know there are probably very few 604 left in the field, but in this case mtspr(xer) looks very much like a superset of isync.
I also just had a look at the documentation of a more widespread core:
https://www.nxp.com/docs/en/reference-manual/MPC7450UM.pdf
and mtspr(xer) is marked as execution and refetch serialized, actually it is the only instruction to have both.
Maybe there is a subtle difference between "refetch serialization" and "pipeline flush", but in this case please educate me.
Besides that the back to back mtctr/mtspr(xer) may limit instruction decoding and issuing bandwidth. I'd rather move one of them up by a few lines since they can only go to one of the execution units on some (or even most?) cores. This was my main point initially.
Gabriel
> > On p9 mtxer is cracked into two latency 3 ops (which run in parallel). > While mtctr has latency 5. > > On p8 mtxer was horrible indeed (but nothing near as bad as a pipeline > flush). > > > Segher
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