Messages in this thread | | | Date | Thu, 24 Feb 2022 13:16:00 -0600 | From | Rob Herring <> | Subject | Re: [PATCH v4 1/5] dt-bindings: clock: Add A7 PLL binding for SDX65 |
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On Tue, 22 Feb 2022 10:26:21 +0530, Rohit Agarwal wrote: > Add information for Cortex A7 PLL clock in Qualcomm > platform SDX65. > > Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> > --- > Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >
Acked-by: Rob Herring <robh@kernel.org>
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