Messages in this thread | | | From | Jim Mattson <> | Date | Wed, 23 Feb 2022 11:50:25 -0800 | Subject | Re: [PATCH 01/11] KVM: x86/pmu: Update comments for AMD gp counters |
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On Mon, Feb 21, 2022 at 3:52 AM Like Xu <like.xu.linux@gmail.com> wrote: > > From: Like Xu <likexu@tencent.com> > > The obsolete comment could more accurately state that AMD platforms > have two base MSR addresses and two different maximum numbers > for gp counters, depending on the X86_FEATURE_PERFCTR_CORE feature. > > Signed-off-by: Like Xu <likexu@tencent.com> > --- > arch/x86/kvm/pmu.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c > index b1a02993782b..c4692f0ff87e 100644 > --- a/arch/x86/kvm/pmu.c > +++ b/arch/x86/kvm/pmu.c > @@ -34,7 +34,7 @@ > * However AMD doesn't support fixed-counters; > * - There are three types of index to access perf counters (PMC): > * 1. MSR (named msr): For example Intel has MSR_IA32_PERFCTRn and AMD > - * has MSR_K7_PERFCTRn. > + * has MSR_F15H_PERF_CTRn or MSR_K7_PERFCTRn.
"Or" sounds exclusive. Maybe it would be better to say:
has MSR_K7_PERFCTRn and, for families 15H and later, MSR_F15H_PERF_CTRn, where MSR_F15H_PERF_CTR[0-3] are aliased to MSR_K7_PERFCTRn.
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