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    Subject[PATCH 5/6] arm64: dts: qcom: sm8150: Add pcie nodes for SM8150
    Date
    Add nodes for the two PCIe controllers founds on the
    SM8150 SoC.

    Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
    Cc: Rob Herring <robh+dt@kernel.org>
    Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
    ---
    arch/arm64/boot/dts/qcom/sm8150.dtsi | 243 +++++++++++++++++++++++++++
    1 file changed, 243 insertions(+)

    diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi
    index 6012322a5984..b97f04ec9c6b 100644
    --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
    +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
    @@ -1626,6 +1626,203 @@ system-cache-controller@9200000 {
    interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
    };

    + pcie0: pci@1c00000 {
    + compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
    + reg = <0 0x01c00000 0 0x3000>,
    + <0 0x60000000 0 0xf1d>,
    + <0 0x60000f20 0 0xa8>,
    + <0 0x60001000 0 0x1000>,
    + <0 0x60100000 0 0x100000>;
    + reg-names = "parf", "dbi", "elbi", "atu", "config";
    + device_type = "pci";
    + linux,pci-domain = <0>;
    + bus-range = <0x00 0xff>;
    + num-lanes = <1>;
    +
    + #address-cells = <3>;
    + #size-cells = <2>;
    +
    + ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
    + <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0x3d00000>;
    +
    + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
    + interrupt-names = "msi";
    + #interrupt-cells = <1>;
    + interrupt-map-mask = <0 0 0 0x7>;
    + interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
    + <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
    + <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
    + <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
    +
    + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
    + <&gcc GCC_PCIE_0_AUX_CLK>,
    + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
    + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
    + <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
    + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
    + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
    + clock-names = "pipe",
    + "aux",
    + "cfg",
    + "bus_master",
    + "bus_slave",
    + "slave_q2a",
    + "tbu";
    +
    + iommus = <&apps_smmu 0x1d80 0x7f>;
    + iommu-map = <0x0 &apps_smmu 0x1d80 0x1>,
    + <0x100 &apps_smmu 0x1d81 0x1>;
    +
    + resets = <&gcc GCC_PCIE_0_BCR>;
    + reset-names = "pci";
    +
    + power-domains = <&gcc PCIE_0_GDSC>;
    +
    + phys = <&pcie0_lane>;
    + phy-names = "pciephy";
    +
    + perst-gpio = <&tlmm 35 GPIO_ACTIVE_HIGH>;
    + enable-gpio = <&tlmm 37 GPIO_ACTIVE_HIGH>;
    +
    + pinctrl-names = "default";
    + pinctrl-0 = <&pcie0_default_state>;
    +
    + status = "disabled";
    + };
    +
    + pcie0_phy: phy@1c06000 {
    + compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy";
    + reg = <0 0x01c06000 0 0x1c0>;
    + #address-cells = <2>;
    + #size-cells = <2>;
    + ranges;
    + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
    + <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
    + <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
    + clock-names = "aux", "cfg_ahb", "refgen";
    +
    + resets = <&gcc GCC_PCIE_0_PHY_BCR>;
    + reset-names = "phy";
    +
    + assigned-clocks = <&gcc GCC_PCIE0_PHY_REFGEN_CLK>;
    + assigned-clock-rates = <100000000>;
    +
    + status = "disabled";
    +
    + pcie0_lane: phy@1c06200 {
    + reg = <0 0x1c06200 0 0x170>, /* tx */
    + <0 0x1c06400 0 0x200>, /* rx */
    + <0 0x1c06800 0 0x1f0>, /* pcs */
    + <0 0x1c06c00 0 0xf4>; /* "pcs_lane" same as pcs_misc? */
    + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
    + clock-names = "pipe0";
    +
    + #phy-cells = <0>;
    + clock-output-names = "pcie_0_pipe_clk";
    + };
    + };
    +
    + pcie1: pci@1c08000 {
    + compatible = "qcom,pcie-sm8150", "snps,dw-pcie";
    + reg = <0 0x01c08000 0 0x3000>,
    + <0 0x40000000 0 0xf1d>,
    + <0 0x40000f20 0 0xa8>,
    + <0 0x40001000 0 0x1000>,
    + <0 0x40100000 0 0x100000>;
    + reg-names = "parf", "dbi", "elbi", "atu", "config";
    + device_type = "pci";
    + linux,pci-domain = <1>;
    + bus-range = <0x00 0xff>;
    + num-lanes = <2>;
    +
    + #address-cells = <3>;
    + #size-cells = <2>;
    +
    + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
    + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
    +
    + interrupts = <GIC_SPI 306 IRQ_TYPE_EDGE_RISING>;
    + interrupt-names = "msi";
    + #interrupt-cells = <1>;
    + interrupt-map-mask = <0 0 0 0x7>;
    + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
    + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
    + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
    + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
    +
    + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
    + <&gcc GCC_PCIE_1_AUX_CLK>,
    + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
    + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
    + <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
    + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
    + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
    + clock-names = "pipe",
    + "aux",
    + "cfg",
    + "bus_master",
    + "bus_slave",
    + "slave_q2a",
    + "tbu";
    +
    + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
    + assigned-clock-rates = <19200000>;
    +
    + iommus = <&apps_smmu 0x1e00 0x7f>;
    + iommu-map = <0x0 &apps_smmu 0x1e00 0x1>,
    + <0x100 &apps_smmu 0x1e01 0x1>;
    +
    + resets = <&gcc GCC_PCIE_1_BCR>;
    + reset-names = "pci";
    +
    + power-domains = <&gcc PCIE_1_GDSC>;
    +
    + phys = <&pcie1_lane>;
    + phy-names = "pciephy";
    +
    + perst-gpio = <&tlmm 102 GPIO_ACTIVE_HIGH>;
    + enable-gpio = <&tlmm 104 GPIO_ACTIVE_HIGH>;
    +
    + pinctrl-names = "default";
    + pinctrl-0 = <&pcie1_default_state>;
    +
    + status = "disabled";
    + };
    +
    + pcie1_phy: phy@1c0e000 {
    + compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy";
    + reg = <0 0x01c0e000 0 0x1c0>;
    + #address-cells = <2>;
    + #size-cells = <2>;
    + ranges;
    + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
    + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
    + <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
    + clock-names = "aux", "cfg_ahb", "refgen";
    +
    + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
    + reset-names = "phy";
    +
    + assigned-clocks = <&gcc GCC_PCIE1_PHY_REFGEN_CLK>;
    + assigned-clock-rates = <100000000>;
    +
    + status = "disabled";
    +
    + pcie1_lane: phy@1c0e200 {
    + reg = <0 0x1c0e200 0 0x170>, /* tx0 */
    + <0 0x1c0e400 0 0x200>, /* rx0 */
    + <0 0x1c0ea00 0 0x1f0>, /* pcs */
    + <0 0x1c0e600 0 0x170>, /* tx1 */
    + <0 0x1c0e800 0 0x200>, /* rx1 */
    + <0 0x1c0ee00 0 0xf4>; /* "pcs_com" same as pcs_misc? */
    + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>;
    + clock-names = "pipe0";
    +
    + #phy-cells = <0>;
    + clock-output-names = "pcie_1_pipe_clk";
    + };
    + };
    +
    ufs_mem_hc: ufshc@1d84000 {
    compatible = "qcom,sm8150-ufshc", "qcom,ufshc",
    "jedec,ufs-2.0";
    @@ -2327,6 +2524,52 @@ qup_spi19_default: qup-spi19-default {
    drive-strength = <6>;
    bias-disable;
    };
    +
    + pcie0_default_state: pcie0-default {
    + perst {
    + pins = "gpio35";
    + function = "gpio";
    + drive-strength = <2>;
    + bias-pull-down;
    + };
    +
    + clkreq {
    + pins = "gpio36";
    + function = "pci_e0";
    + drive-strength = <2>;
    + bias-pull-up;
    + };
    +
    + wake {
    + pins = "gpio37";
    + function = "gpio";
    + drive-strength = <2>;
    + bias-pull-up;
    + };
    + };
    +
    + pcie1_default_state: pcie1-default {
    + perst {
    + pins = "gpio102";
    + function = "gpio";
    + drive-strength = <2>;
    + bias-pull-down;
    + };
    +
    + clkreq {
    + pins = "gpio103";
    + function = "pci_e1";
    + drive-strength = <2>;
    + bias-pull-up;
    + };
    +
    + wake {
    + pins = "gpio104";
    + function = "gpio";
    + drive-strength = <2>;
    + bias-pull-up;
    + };
    + };
    };

    remoteproc_mpss: remoteproc@4080000 {
    --
    2.35.1
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