Messages in this thread | | | From | Radha Chintakuntla <> | Subject | RE: [EXT] Re: [PATCH 0/4] soc: Add support for Marvell OcteonTX2 SDP block | Date | Tue, 22 Feb 2022 19:52:13 +0000 |
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> -----Original Message----- > From: Radha Chintakuntla > Sent: Thursday, February 10, 2022 2:55 PM > To: Arnd Bergmann <arnd@arndb.de> > Cc: Linux ARM <linux-arm-kernel@lists.infradead.org>; Linus Walleij > <linus.walleij@linaro.org>; Linux Kernel Mailing List <linux- > kernel@vger.kernel.org>; Satananda Burla <sburla@marvell.com> > Subject: RE: [EXT] Re: [PATCH 0/4] soc: Add support for Marvell OcteonTX2 > SDP block > > > > > -----Original Message----- > > From: Arnd Bergmann <arnd@arndb.de> > > Sent: Thursday, February 10, 2022 8:30 AM > > To: Radha Chintakuntla <radhac@marvell.com> > > Cc: Linux ARM <linux-arm-kernel@lists.infradead.org>; Arnd Bergmann > > <arnd@arndb.de>; Linus Walleij <linus.walleij@linaro.org>; Linux > > Kernel Mailing List <linux-kernel@vger.kernel.org>; Satananda Burla > > <sburla@marvell.com> > > Subject: [EXT] Re: [PATCH 0/4] soc: Add support for Marvell OcteonTX2 > > SDP block > > > > External Email > > > > ---------------------------------------------------------------------- > > On Wed, Feb 9, 2022 at 11:42 PM Radha Mohan Chintakuntla > > <radhac@marvell.com> wrote: > > > > > > The Marvell OcteonTX2's SDP block is a interface for sending and > > > receiving ethernet packets over the PCIe interface when OcteonTX2 is > > > in PCIe endpoint mode. It interfaces with the OcteonTX2's NIX block > > queues. > > > > Hi Radha, > > > > I'm not sure drivers/soc/ is the right place for it. I have not done > > an actual review so far, but I have some high-level questions to clarify how > this fits in: > > > > When you say it is meant for passing ethernet packets, why is it not > > an ethernet driver? > > The SDP block sits in between the PCI Endpoint controller and the Network > block (NIX). It does an implicit DMA from a remote host to Octeon and has > queues to direct to the NIX queues. The host side will have a netdev driver > which sends/receives packets on the SDP queues so they make it to the NIX. > SDP driver doesn't do any packet transmit or receive by itself so that's why it > is not a netdev driver. > > > > > If this drives the PCIe endpoint mode, how does it interface with the > > pci endpoint framework? It looks like a normal PCI driver. > The block does not drive the endpoint mode as such. The driver is just > settings up the connection between SDP and NIX. It doesn't touch any of the > endpoint registers or setup the endpoint connection. Most of that is done by > firmware which detects the mode and sets up the EP controller. > > > > What hardware does this run on? Is this only usable when both the host > > side and the endpoint side are Octexon TX2 machines with their packet > > engines, or can one of the two be a different machine that has PCIe > > host or endpoint device support? > It runs on Marvell OcteonTX2 when is in PCIe Endpoint. But the host can be > anything - we have tested on x86 and arm64 hosts so far. > The host side will have a netdev driver that will go into the drivers/net area. > > Hi Arnd, Any more information you need on this ?
Regards, Radha
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