Messages in this thread | | | From | "Zhang, Tianfei" <> | Subject | RE: [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar space. | Date | Mon, 21 Feb 2022 07:48:32 +0000 |
| |
> -----Original Message----- > From: Wu, Hao <hao.wu@intel.com> > Sent: Wednesday, February 16, 2022 11:38 AM > To: Zhang, Tianfei <tianfei.zhang@intel.com>; trix@redhat.com; > mdf@kernel.org; Xu, Yilun <yilun.xu@intel.com>; linux-fpga@vger.kernel.org; > linux-doc@vger.kernel.org; linux-kernel@vger.kernel.org > Cc: corbet@lwn.net; Matthew Gerlach <matthew.gerlach@linux.intel.com> > Subject: Re: [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar space. > > > Subject: [PATCH v1 3/7] fpga: dfl: Allow for ports with no local bar space. > > > > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > > > From a fpga partial reconfiguration standpoint, a port may not be > > connected any local BAR space. The port could be connected to a > > different PCIe Physical Function (PF) or Virtual Function (VF), in > > which case another driver instance would manage the endpoint. > > > > Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com> > > --- > > drivers/fpga/dfl-pci.c | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/drivers/fpga/dfl-pci.c b/drivers/fpga/dfl-pci.c index > > 4d68719e608f..8abd9b408403 100644 > > --- a/drivers/fpga/dfl-pci.c > > +++ b/drivers/fpga/dfl-pci.c > > @@ -243,6 +243,7 @@ static int find_dfls_by_default(struct pci_dev *pcidev, > > v = readq(base + FME_HDR_CAP); > > port_num = FIELD_GET(FME_CAP_NUM_PORTS, v); > > > > + dev_info(&pcidev->dev, "port_num = %d\n", port_num); > > Do we really need this info here? in FME there is one sysfs interface for port > num.
I think it is not necessary, I will remove it.
> > > WARN_ON(port_num > MAX_DFL_FPGA_PORT_NUM); > > > > for (i = 0; i < port_num; i++) { > > @@ -258,6 +259,13 @@ static int find_dfls_by_default(struct pci_dev *pcidev, > > */ > > bar = FIELD_GET(FME_PORT_OFST_BAR_ID, v); > > offset = FIELD_GET(FME_PORT_OFST_DFH_OFST, v); > > + if (bar >= PCI_STD_NUM_BARS) { > > + dev_info(&pcidev->dev, "skipping port without > > local BAR space %d\n", > > + bar); > > + continue; > > Is this change for IOFS? From patch #1, we have FME and PORT on PF0, so we > should have a BAR for PORT on PF0, is my understanding correct?
Yes, we have a Port device on each PR slot in IOFS, but for " Multiple VFs per PR slot" model, the Port device would not connected to AFU/PR slot (the BarID of Port device should be set to invalid), and we just can access PR slot/AFU resource via VFs.
> > Thanks > Hao > > > + } else { > > + dev_info(&pcidev->dev, "BAR %d offset %u\n", > > bar, offset); > > + } > > start = pci_resource_start(pcidev, bar) + offset; > > len = pci_resource_len(pcidev, bar) - offset; > > > > -- > > 2.17.1
| |