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    Subject[PATCH v2 13/15] clk: mediatek: Add MT8186 camsys clock support
    Date
    Add MT8186 camsys clock controllers which provide clock gate
    control for camera IP blocks.

    Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
    Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
    ---
    drivers/clk/mediatek/Makefile | 3 +-
    drivers/clk/mediatek/clk-mt8186-cam.c | 90 +++++++++++++++++++++++++++
    2 files changed, 92 insertions(+), 1 deletion(-)
    create mode 100644 drivers/clk/mediatek/clk-mt8186-cam.c

    diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
    index 28aefad8042e..3ad27f94eeef 100644
    --- a/drivers/clk/mediatek/Makefile
    +++ b/drivers/clk/mediatek/Makefile
    @@ -74,7 +74,8 @@ obj-$(CONFIG_COMMON_CLK_MT8183_VENCSYS) += clk-mt8183-venc.o
    obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt8186-infra_ao.o \
    clk-mt8186-apmixedsys.o clk-mt8186-imp_iic_wrap.o \
    clk-mt8186-mfg.o clk-mt8186-mm.o clk-mt8186-wpe.o \
    - clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o
    + clk-mt8186-img.o clk-mt8186-vdec.o clk-mt8186-venc.o \
    + clk-mt8186-cam.o
    obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
    obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
    obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
    diff --git a/drivers/clk/mediatek/clk-mt8186-cam.c b/drivers/clk/mediatek/clk-mt8186-cam.c
    new file mode 100644
    index 000000000000..6053f0faded7
    --- /dev/null
    +++ b/drivers/clk/mediatek/clk-mt8186-cam.c
    @@ -0,0 +1,90 @@
    +// SPDX-License-Identifier: GPL-2.0-only
    +//
    +// Copyright (c) 2022 MediaTek Inc.
    +// Author: Chun-Jie Chen <chun-jie.chen@mediatek.com>
    +
    +#include "clk-gate.h"
    +#include "clk-mtk.h"
    +
    +#include <dt-bindings/clock/mt8186-clk.h>
    +#include <linux/clk-provider.h>
    +#include <linux/platform_device.h>
    +
    +static const struct mtk_gate_regs cam_cg_regs = {
    + .set_ofs = 0x4,
    + .clr_ofs = 0x8,
    + .sta_ofs = 0x0,
    +};
    +
    +#define GATE_CAM(_id, _name, _parent, _shift) \
    + GATE_MTK(_id, _name, _parent, &cam_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
    +
    +static const struct mtk_gate cam_clks[] = {
    + GATE_CAM(CLK_CAM_LARB13, "cam_larb13", "top_cam", 0),
    + GATE_CAM(CLK_CAM_DFP_VAD, "cam_dfp_vad", "top_cam", 1),
    + GATE_CAM(CLK_CAM_LARB14, "cam_larb14", "top_cam", 2),
    + GATE_CAM(CLK_CAM, "cam", "top_cam", 6),
    + GATE_CAM(CLK_CAMTG, "camtg", "top_cam", 7),
    + GATE_CAM(CLK_CAM_SENINF, "cam_seninf", "top_cam", 8),
    + GATE_CAM(CLK_CAMSV1, "camsv1", "top_cam", 10),
    + GATE_CAM(CLK_CAMSV2, "camsv2", "top_cam", 11),
    + GATE_CAM(CLK_CAMSV3, "camsv3", "top_cam", 12),
    + GATE_CAM(CLK_CAM_CCU0, "cam_ccu0", "top_cam", 13),
    + GATE_CAM(CLK_CAM_CCU1, "cam_ccu1", "top_cam", 14),
    + GATE_CAM(CLK_CAM_MRAW0, "cam_mraw0", "top_cam", 15),
    + GATE_CAM(CLK_CAM_FAKE_ENG, "cam_fake_eng", "top_cam", 17),
    + GATE_CAM(CLK_CAM_CCU_GALS, "cam_ccu_gals", "top_cam", 18),
    + GATE_CAM(CLK_CAM2MM_GALS, "cam2mm_gals", "top_cam", 19),
    +};
    +
    +static const struct mtk_gate cam_rawa_clks[] = {
    + GATE_CAM(CLK_CAM_RAWA_LARBX_RAWA, "cam_rawa_larbx_rawa", "top_cam", 0),
    + GATE_CAM(CLK_CAM_RAWA, "cam_rawa", "top_cam", 1),
    + GATE_CAM(CLK_CAM_RAWA_CAMTG_RAWA, "cam_rawa_camtg_rawa", "top_cam", 2),
    +};
    +
    +static const struct mtk_gate cam_rawb_clks[] = {
    + GATE_CAM(CLK_CAM_RAWB_LARBX_RAWB, "cam_rawb_larbx_rawb", "top_cam", 0),
    + GATE_CAM(CLK_CAM_RAWB, "cam_rawb", "top_cam", 1),
    + GATE_CAM(CLK_CAM_RAWB_CAMTG_RAWB, "cam_rawb_camtg_rawb", "top_cam", 2),
    +};
    +
    +static const struct mtk_clk_desc cam_desc = {
    + .clks = cam_clks,
    + .num_clks = ARRAY_SIZE(cam_clks),
    +};
    +
    +static const struct mtk_clk_desc cam_rawa_desc = {
    + .clks = cam_rawa_clks,
    + .num_clks = ARRAY_SIZE(cam_rawa_clks),
    +};
    +
    +static const struct mtk_clk_desc cam_rawb_desc = {
    + .clks = cam_rawb_clks,
    + .num_clks = ARRAY_SIZE(cam_rawb_clks),
    +};
    +
    +static const struct of_device_id of_match_clk_mt8186_cam[] = {
    + {
    + .compatible = "mediatek,mt8186-camsys",
    + .data = &cam_desc,
    + }, {
    + .compatible = "mediatek,mt8186-camsys_rawa",
    + .data = &cam_rawa_desc,
    + }, {
    + .compatible = "mediatek,mt8186-camsys_rawb",
    + .data = &cam_rawb_desc,
    + }, {
    + /* sentinel */
    + }
    +};
    +
    +static struct platform_driver clk_mt8186_cam_drv = {
    + .probe = mtk_clk_simple_probe,
    + .remove = mtk_clk_simple_remove,
    + .driver = {
    + .name = "clk-mt8186-cam",
    + .of_match_table = of_match_clk_mt8186_cam,
    + },
    +};
    +builtin_platform_driver(clk_mt8186_cam_drv);
    --
    2.18.0
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