Messages in this thread | | | From | Andreas Schwab <> | Subject | Re: [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without correct XLEN | Date | Thu, 10 Feb 2022 22:58:09 +0100 |
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On Feb 10 2022, Atish Patra wrote:
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 469b9739faf7..cca579bae8a0 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void) > for_each_of_cpu_node(node) { > unsigned long this_hwcap = 0; > uint64_t this_isa = 0; > + char *temp; > > if (riscv_of_processor_hartid(node) < 0) > continue; > @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void) > continue; > } > > + temp = (char *)isa;
There should be no need for this cast.
-- Andreas Schwab, schwab@linux-m68k.org GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1 "And now for something completely different."
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