Messages in this thread Patch in this message | | | From | Manivannan Sadhasivam <> | Subject | [PATCH 01/12] dt-bindings: arm: msm: Update the maintainers for LLCC | Date | Wed, 7 Dec 2022 19:29:10 +0530 |
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Rishabh Bhatnagar has left Qualcomm, and there is no evidence of him maintaining with a new identity. So his entry needs to be removed.
Also, Sai Prakash Ranjan's email address should be updated to use quicinc domain.
Cc: Sai Prakash Ranjan <quic_saipraka@quicinc.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..d1df49ffcc1b 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar <rishabhb@codeaurora.org> - - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> + - Sai Prakash Ranjan <quic_saipraka@quicinc.com> description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, -- 2.25.1
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