Messages in this thread | | | From | Ulf Hansson <> | Date | Wed, 7 Dec 2022 13:37:32 +0100 | Subject | Re: [PATCH] mmc: sdhci-of-esdhc: limit the SDHC clock frequency |
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On Fri, 2 Dec 2022 at 08:44, <andy.tang@nxp.com> wrote: > > From: Andy Tang <andy.tang@nxp.com> > > The highest clock frequency for eMMC HS200 mode on ls1043a > is 116.7Mhz according to its specification. > So add the limit to gate the frequency. > > Signed-off-by: Andy Tang <andy.tang@nxp.com>
Applied for next, thanks!
Kind regards Uffe
> --- > v2: change the author to andy tang > > drivers/mmc/host/sdhci-of-esdhc.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c > index 00542dd74c07..1fd4ae10862d 100644 > --- a/drivers/mmc/host/sdhci-of-esdhc.c > +++ b/drivers/mmc/host/sdhci-of-esdhc.c > @@ -43,6 +43,12 @@ static const struct esdhc_clk_fixup ls1021a_esdhc_clk = { > .max_clk[MMC_TIMING_SD_HS] = 46500000, > }; > > +static const struct esdhc_clk_fixup ls1043a_esdhc_clk = { > + .sd_dflt_max_clk = 25000000, > + .max_clk[MMC_TIMING_UHS_SDR104] = 116700000, > + .max_clk[MMC_TIMING_MMC_HS200] = 116700000, > +}; > + > static const struct esdhc_clk_fixup ls1046a_esdhc_clk = { > .sd_dflt_max_clk = 25000000, > .max_clk[MMC_TIMING_UHS_SDR104] = 167000000, > @@ -64,6 +70,7 @@ static const struct esdhc_clk_fixup p1010_esdhc_clk = { > > static const struct of_device_id sdhci_esdhc_of_match[] = { > { .compatible = "fsl,ls1021a-esdhc", .data = &ls1021a_esdhc_clk}, > + { .compatible = "fsl,ls1043a-esdhc", .data = &ls1043a_esdhc_clk}, > { .compatible = "fsl,ls1046a-esdhc", .data = &ls1046a_esdhc_clk}, > { .compatible = "fsl,ls1012a-esdhc", .data = &ls1012a_esdhc_clk}, > { .compatible = "fsl,p1010-esdhc", .data = &p1010_esdhc_clk}, > -- > 2.25.1 >
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