Messages in this thread | | | Date | Thu, 29 Dec 2022 11:57:03 +0200 | From | Andy Shevchenko <> | Subject | Re: [PATCH v8 3/4] fpga: dfl: add basic support for DFHv1 |
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On Wed, Dec 28, 2022 at 10:16:23AM -0800, matthew.gerlach@linux.intel.com wrote: > From: Matthew Gerlach <matthew.gerlach@linux.intel.com> > > Version 1 of the Device Feature Header (DFH) definition adds > functionality to the DFL bus. > > A DFHv1 header may have one or more parameter blocks that > further describes the HW to SW. Add support to the DFL bus
Single space is enough.
> to parse the MSI-X parameter. > > The location of a feature's register set is explicitly > described in DFHv1 and can be relative to the base of the DFHv1 > or an absolute address. Parse the location and pass the information > to DFL driver.
I'm wondering what DFL states for.
...
> +/** > + * dfh_get_u64_param_vals() - get array of u64 param values for given parameter id > + * @dfl_dev: dfl device > + * @param: id of dfl parameter > + * @pval: location of parameter data destination > + * @nvals: number of u64 elements of parameter data > + * > + * Return: pointer to start of parameter block, PTR_ERR otherwise > + */ > +u64 *dfh_get_u64_param_vals(struct dfl_device *dfl_dev, int param_id, u64 *pval, int nvals) > +{ > + u64 *param = find_param(dfl_dev->params, dfl_dev->param_size, param_id); > + u64 next; > + int i; > + > + if (!param) > + return ERR_PTR(-ENOENT); > + > + next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, *param); > + > + if (nvals >= next) > + return ERR_PTR(-ENOMEM);
ENODATA ?
> + for (i = 0; i < nvals; i++) > + *pval++ = param[i + 1];
memcpy() ?
> + return param; > +}
...
> + finfo = kzalloc(struct_size(finfo, params, dfh_psize/sizeof(u64)), GFP_KERNEL);
' / ' (mind the spaces)
Also, perhaps better to use sizeof(*params) or what is the member of that structure. So it will be more robust against possible changes.
> if (!finfo) > return -ENOMEM;
-- With Best Regards, Andy Shevchenko
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