Messages in this thread | | | From | "Lad, Prabhakar" <> | Date | Wed, 28 Dec 2022 23:29:43 +0000 | Subject | Re: [PATCH] clocksource/drivers/riscv: Increase the clock source rating |
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Hi Samuel,
Thank you for the patch.
On Wed, Dec 28, 2022 at 12:44 AM Samuel Holland <samuel@sholland.org> wrote: > > RISC-V provides an architectural clock source via the time CSR. This > clock source exposes a 64-bit counter synchronized across all CPUs. > Because it is accessed using a CSR, it is much more efficient to read > than MMIO clock sources. For example, on the Allwinner D1, reading the > sun4i timer in a loop takes 131 cycles/iteration, while reading the > RISC-V time CSR takes only 5 cycles/iteration. > > Adjust the RISC-V clock source rating so it is preferred over the > various platform-specific MMIO clock sources. > > Signed-off-by: Samuel Holland <samuel@sholland.org> > --- > > drivers/clocksource/timer-riscv.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Cheers, Prabhakar
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > index a0d66fabf073..55dad7965f43 100644 > --- a/drivers/clocksource/timer-riscv.c > +++ b/drivers/clocksource/timer-riscv.c > @@ -73,7 +73,7 @@ static u64 notrace riscv_sched_clock(void) > > static struct clocksource riscv_clocksource = { > .name = "riscv_clocksource", > - .rating = 300, > + .rating = 400, > .mask = CLOCKSOURCE_MASK(64), > .flags = CLOCK_SOURCE_IS_CONTINUOUS, > .read = riscv_clocksource_rdtime, > -- > 2.37.4 >
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