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    Subject[PATCH v2 9/9] arm64: dts: renesas: rzg2ul-smarc-som: Add PHY interrupt support for ETH{0/1}
    Date
    From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

    The PHY interrupt (INT_N) pin is connected to IRQ2 and IRQ7 for ETH0 and
    ETH1 respectively.

    Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    ---
    v1 -> v2
    * No change
    ---
    arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi | 11 +++++++++--
    1 file changed, 9 insertions(+), 2 deletions(-)

    diff --git a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
    index 931efc07d6fb..49ecd33aeeb8 100644
    --- a/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
    +++ b/arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi
    @@ -6,6 +6,7 @@
    */

    #include <dt-bindings/gpio/gpio.h>
    +#include <dt-bindings/interrupt-controller/irqc-rzg2l.h>
    #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>

    / {
    @@ -77,6 +78,8 @@ phy0: ethernet-phy@7 {
    compatible = "ethernet-phy-id0022.1640",
    "ethernet-phy-ieee802.3-c22";
    reg = <7>;
    + interrupt-parent = <&irqc>;
    + interrupts = <RZG2L_IRQ2 IRQ_TYPE_LEVEL_LOW>;
    rxc-skew-psec = <2400>;
    txc-skew-psec = <2400>;
    rxdv-skew-psec = <0>;
    @@ -104,6 +107,8 @@ phy1: ethernet-phy@7 {
    compatible = "ethernet-phy-id0022.1640",
    "ethernet-phy-ieee802.3-c22";
    reg = <7>;
    + interrupt-parent = <&irqc>;
    + interrupts = <RZG2L_IRQ7 IRQ_TYPE_LEVEL_LOW>;
    rxc-skew-psec = <2400>;
    txc-skew-psec = <2400>;
    rxdv-skew-psec = <0>;
    @@ -151,7 +156,8 @@ eth0_pins: eth0 {
    <RZG2L_PORT_PINMUX(3, 2, 1)>, /* ET0_RXD0 */
    <RZG2L_PORT_PINMUX(3, 3, 1)>, /* ET0_RXD1 */
    <RZG2L_PORT_PINMUX(4, 0, 1)>, /* ET0_RXD2 */
    - <RZG2L_PORT_PINMUX(4, 1, 1)>; /* ET0_RXD3 */
    + <RZG2L_PORT_PINMUX(4, 1, 1)>, /* ET0_RXD3 */
    + <RZG2L_PORT_PINMUX(5, 1, 7)>; /* IRQ2 */
    };

    eth1_pins: eth1 {
    @@ -169,7 +175,8 @@ eth1_pins: eth1 {
    <RZG2L_PORT_PINMUX(9, 1, 1)>, /* ET1_RXD0 */
    <RZG2L_PORT_PINMUX(9, 2, 1)>, /* ET1_RXD1 */
    <RZG2L_PORT_PINMUX(9, 3, 1)>, /* ET1_RXD2 */
    - <RZG2L_PORT_PINMUX(10, 0, 1)>; /* ET1_RXD3 */
    + <RZG2L_PORT_PINMUX(10, 0, 1)>, /* ET1_RXD3 */
    + <RZG2L_PORT_PINMUX(18, 5, 1)>; /* IRQ7 */
    };

    sdhi0_emmc_pins: sd0emmc {
    --
    2.25.1
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