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Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 Subject: Re: [RESEND PATCH RFC V4 0/3] Generate device tree node for pci devices Content-Language: en-US To: Rob Herring Cc: , , , , , , , , <20221201212009.GB1225112-robh@kernel.org> From: Lizhi Hou In-Reply-To: <20221201212009.GB1225112-robh@kernel.org> X-EOPAttributedMessage: 0 x-ms-publictraffictype: Email x-ms-traffictypediagnostic: CY4PEPF0000C96A:EE_|SA3PR12MB7901:EE_ x-ms-office365-filtering-correlation-id: 95ae41b2-58e1-4b64-6efa-08dad4877b7c x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: MjXF360lEskQ4klmAIc4v3a8tqB3QRsPB0gspNFW1yV6qShm3WKLEGabvu/fTNKkf04aa03Fd36CtNPzgqrIRfxDzMY2Ehmz7MyNmx+Hc4hxgnzKdauFfAOjSzN9jIH/HfW2o8kCKAXrz+Ie1ciu1Pt9uBpdRJPgikRrBu7BI3yUMG/+WDOdlv5QjfrCCGphIYkMAotrVjM5RNkOdtue1G8z4mWA8ApmjfUSe4Sge/7myoM5OzH/yWnlzJmszC X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(396003)(376002)(39860400002)(346002)(136003)(451199015)(40470700004)(36840700001)(46966006)(26005)(36860700001)( X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Dec 2022 17:05:58.2834 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 95ae41b2-58e1-4b64-6efa-08dad4877b7c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000C96A.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7901 Precedence: bulk List-Id: X-Mailing-List: linux-kernel@vger.kernel.org --------------DyzxPEhU3RGp1T525PVZ00Hq Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit On 12/1/22 13:20, Rob Herring wrote: > On Mon, Nov 21, 2022 at 08:43:01AM -0800, Lizhi Hou wrote: >> This patch series introduces OF overlay support for PCI devices which >> primarily addresses two use cases. First, it provides a data driven method >> to describe hardware peripherals that are present in a PCI endpoint and >> hence can be accessed by the PCI host. Second, it allows reuse of a OF >> compatible driver -- often used in SoC platforms -- in a PCI host based >> system. >> >> There are 2 series devices rely on this patch: >> >> 1) Xilinx Alveo Accelerator cards (FPGA based device) >> 2) Microchip LAN9662 Ethernet Controller >> >> Please see: https://lore.kernel.org/lkml/20220427094502.456111-1-clement.leger@bootlin.com/ >> >> Normally, the PCI core discovers PCI devices and their BARs using the >> PCI enumeration process. However, the process does not provide a way to >> discover the hardware peripherals that are present in a PCI device, and >> which can be accessed through the PCI BARs. Also, the enumeration process >> does not provide a way to associate MSI-X vectors of a PCI device with the >> hardware peripherals that are present in the device. PCI device drivers >> often use header files to describe the hardware peripherals and their >> resources as there is no standard data driven way to do so. This patch >> series proposes to use flattened device tree blob to describe the >> peripherals in a data driven way. Based on previous discussion, using >> device tree overlay is the best way to unflatten the blob and populate >> platform devices. To use device tree overlay, there are three obvious >> problems that need to be resolved. >> >> First, we need to create a base tree for non-DT system such as x86_64. A >> patch series has been submitted for this: >> https://lore.kernel.org/lkml/20220624034327.2542112-1-frowand.list@gmail.com/ >> https://lore.kernel.org/lkml/20220216050056.311496-1-lizhi.hou@xilinx.com/ >> >> Second, a device tree node corresponding to the PCI endpoint is required >> for overlaying the flattened device tree blob for that PCI endpoint. >> Because PCI is a self-discoverable bus, a device tree node is usually not >> created for PCI devices. This series adds support to generate a device >> tree node for a PCI device which advertises itself using PCI quirks >> infrastructure. >> >> Third, we need to generate device tree nodes for PCI bridges since a child >> PCI endpoint may choose to have a device tree node created. >> >> This patch series is made up of three patches. >> >> The first patch is adding OF interface to create or destroy OF node >> dynamically. >> >> The second patch introduces a kernel option, CONFIG_DYNAMIC_PCI_OF_NODEX. >> When the option is turned on, the kernel will generate device tree nodes >> for all PCI bridges unconditionally. The patch also shows how to use the >> PCI quirks infrastructure, DECLARE_PCI_FIXUP_FINAL to generate a device >> tree node for a device. Specifically, the patch generates a device tree >> node for Xilinx Alveo U50 PCIe accelerator device. The generated device >> tree nodes do not have any property. >> >> The third patch adds basic properties ('reg', 'compatible' and >> 'device_type') to the dynamically generated device tree nodes. More >> properties can be added in the future. >> >> Here is the example of device tree nodes generated within the ARM64 QEMU. > Can you share the setup for QEMU. I attached the VM xml config file. Should I include the configure in cover letter next time? > > >> # lspci -t >> -[0000:00]-+-00.0 >> +-01.0-[01]-- >> +-01.1-[02]----00.0 >> +-01.2-[03]----00.0 >> +-01.3-[04]----00.0 >> +-01.4-[05]----00.0 >> +-01.5-[06]-- >> +-01.6-[07]-- >> +-01.7-[08]-- >> +-02.0-[09-0b]----00.0-[0a-0b]----00.0-[0b]--+-00.0 >> | \-00.1 >> +-02.1-[0c]-- >> \-03.0-[0d-0e]----00.0-[0e]----01.0 >> >> # tree /sys/firmware/devicetree/base/pcie\@10000000 >> /sys/firmware/devicetree/base/pcie@10000000 >> |-- #address-cells >> |-- #interrupt-cells >> |-- #size-cells >> |-- bus-range >> |-- compatible >> |-- device_type >> |-- dma-coherent >> |-- interrupt-map >> |-- interrupt-map-mask >> |-- linux,pci-domain >> |-- msi-parent >> |-- name >> |-- pci@1,0 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- ranges >> | `-- reg >> |-- pci@1,1 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- ranges >> | `-- reg >> |-- pci@1,2 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- ranges >> | `-- reg >> |-- pci@1,3 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- ranges >> | `-- reg >> |-- pci@1,4 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- ranges >> | `-- reg >> |-- pci@1,5 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- ranges >> | `-- reg >> |-- pci@1,6 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- ranges >> | `-- reg >> |-- pci@1,7 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- ranges >> | `-- reg >> |-- pci@2,0 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- pci@0,0 >> | | |-- #address_cells >> | | |-- #size_cells >> | | |-- compatible >> | | |-- device_type >> | | |-- pci@0,0 >> | | | |-- #address_cells >> | | | |-- #size_cells >> | | | |-- compatible >> | | | |-- dev@0,0 > I don't see anywhere in the patch series defining 'dev'. It is defined here: > +void of_pci_make_dev_node(struct pci_dev *pdev) > +{ > +    struct device_node *parent, *dt_node = NULL; > +    const char *pci_type = "dev"; Thanks, Lizhi > >> | | | | |-- compatible >> | | | | `-- reg >> | | | |-- dev@0,1 >> | | | | |-- compatible >> | | | | `-- reg >> | | | |-- device_type >> | | | |-- ranges >> | | | `-- reg >> | | |-- ranges >> | | `-- reg >> | |-- ranges >> | `-- reg >> |-- pci@2,1 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- ranges >> | `-- reg >> |-- pci@3,0 >> | |-- #address_cells >> | |-- #size_cells >> | |-- compatible >> | |-- device_type >> | |-- pci@0,0 >> | | |-- #address_cells >> | | |-- #size_cells >> | | |-- compatible >> | | |-- device_type >> | | |-- ranges >> | | `-- reg >> | |-- ranges >> | `-- reg >> |-- ranges >> `-- reg >> >> Changes since RFC v3: >> - Split the Xilinx Alveo U50 PCI quirk to a separate patch >> - Minor changes in commit description and code comment >> >> Changes since RFC v2: >> - Merged patch 3 with patch 2 >> - Added OF interfaces of_changeset_add_prop_* and use them to create >> properties. >> - Added '#address-cells', '#size-cells' and 'ranges' properties. >> >> Changes since RFC v1: >> - Added one patch to create basic properties. >> - To move DT related code out of PCI subsystem, replaced of_node_alloc() >> with of_create_node()/of_destroy_node() >> >> Lizhi Hou (3): >> of: dynamic: Add interfaces for creating device node dynamically >> PCI: Create device tree node for selected devices >> PCI: Add PCI quirks to generate device tree node for Xilinx Alveo U50 >> >> drivers/of/dynamic.c | 187 ++++++++++++++++++++++++++ >> drivers/pci/Kconfig | 12 ++ >> drivers/pci/Makefile | 1 + >> drivers/pci/bus.c | 2 + >> drivers/pci/msi/irqdomain.c | 6 +- >> drivers/pci/of.c | 71 ++++++++++ >> drivers/pci/of_property.c | 256 ++++++++++++++++++++++++++++++++++++ >> drivers/pci/pci-driver.c | 3 +- >> drivers/pci/pci.h | 19 +++ >> drivers/pci/quirks.c | 11 ++ >> drivers/pci/remove.c | 1 + >> include/linux/of.h | 24 ++++ >> 12 files changed, 590 insertions(+), 3 deletions(-) >> create mode 100644 drivers/pci/of_property.c >> >> -- >> 2.17.1 >> >> --------------DyzxPEhU3RGp1T525PVZ00Hq Content-Type: text/xml; charset="UTF-8"; name="arm64-vm.xml" Content-Disposition: attachment; filename="arm64-vm.xml" Content-Transfer-Encoding: base64 PGRvbWFpbiB0eXBlPSdxZW11Jz4KICA8bmFtZT5hcm02NC12bTwvbmFtZT4KICA8dXVpZD41 M2Q4MTllZi1kNjI4LTQzMzctOWEyMS0xNDQ2OGU2YzQ0MzY8L3V1aWQ+CiAgPG1lbW9yeSB1 bml0PSdLaUInPjIwOTcxNTI8L21lbW9yeT4KICA8Y3VycmVudE1lbW9yeSB1bml0PSdLaUIn PjIwOTcxNTI8L2N1cnJlbnRNZW1vcnk+CiAgPHZjcHUgcGxhY2VtZW50PSdzdGF0aWMnPjI8 L3ZjcHU+CiAgPG9zPgogICAgPHR5cGUgYXJjaD0nYWFyY2g2NCcgbWFjaGluZT0ndmlydC0y LjExJz5odm08L3R5cGU+CiAgICA8a2VybmVsPi9yb290L3BjaWUtZHQtaW1hZ2VzL3ZtbGlu dXotNi4wLjAtcmM1Kzwva2VybmVsPgogICAgPGluaXRyZD4vcm9vdC9wY2llLWR0LWltYWdl cy9pbml0cmQuaW1nLTYuMC4wLXJjNSs8L2luaXRyZD4KICAgIDxjbWRsaW5lPmNvbnNvbGU9 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