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    Subject[PATCH v3 00/11] Basic clock and reset support for StarFive JH7110 RISC-V SoC
    Date
    This patch series adds basic clock&reset support for StarFive JH7110 SoC.
    You can simply get or review the patches at the link [1].

    [1]: https://github.com/hal-feng/linux/commits/visionfive2-minimal

    Changes since v2:
    - Rebased on tag v6.1.
    - Added "JH71X0" to the StarFive driver headers in MAINTAINERS.
    - Removed Co-developed-by tag of Hal in patch 1 and patch 4.
    - Changed the commit author from Hal to Emil in patch 2 and patch 5.
    Removed Co-developed-by tag of Emil in patch 2 and patch 5. (by Emil)
    - Improved the coding style of patch 11, 12 and 13.
    - Dropped patch 14. (by Emil)
    Patch 4:
    - Passed the "owner" member of reset_controller_dev structure
    directly in reset_starfive_jh7100_register(). (by Emil)
    - Added MAINTAINERS changes.
    Patch 7:
    - Split patch 7 into sys part and aon part. Merged them into patch 9 and
    patch 10 respectively. (by Krzysztof)
    - Renamed include/dt-bindings/clock/starfive-jh7110.h to
    include/dt-bindings/clock/starfive,jh7110-crg.h. (by Krzysztof)
    - Synchronized the definitions with the latest changes from Emil.
    Patch 8:
    - Split patch 8 into sys part and aon part. Merged them into patch 9 and
    patch 10 respectively. (by Krzysztof)
    - Renamed include/dt-bindings/reset/starfive-jh7110.h to
    include/dt-bindings/reset/starfive,jh7110-crg.h. (by Krzysztof)
    - Fixed the date of Copyright. (by Emil)
    - Dropped weird indentations. (by Krzysztof)
    - Synchronized the definitions with the latest changes from Emil.
    Patch 9:
    - Improved the description of clocks. (by Emil and Krzysztof)
    - Added MAINTAINERS changes.
    Patch 10:
    - Improved the description of clocks. (by Emil and Krzysztof)
    - Changed the clock-name "clk_rtc" to "rtc_osc" and "apb_bus_func" to
    "apb_bus".
    Patch 11:
    - Removed the flags of trace/debug clocks and set the flags of core clocks
    as CLK_IS_CRITICAL. (by Emil)
    - Deleted the extra 1-1 clocks and synchronized the clock tree with the
    latest changes from Emil. (by Emil)
    - Selected RESET_STARFIVE_JH7110 in Kconfig option CLK_STARFIVE_JH7110_SYS.
    Patch 12:
    - Changed the macro JH7110_AONCLK_RTC to JH7110_AONCLK_RTC_OSC and
    JH7110_AONCLK_APB_BUS_FUNC to JH7110_AONCLK_APB_BUS.
    - Synchronized the clock tree with the latest changes from Emil.
    - Set the MODULE_LICENSE as "GPL" according to commit bf7fbeeae6db.
    Patch 13:
    - Removed the "asserted" member in reset_info structure and always pass
    NULL when calling reset_starfive_jh71x0_register(). (by Emil)

    v2: https://lore.kernel.org/all/20221118010627.70576-1-hal.feng@starfivetech.com/

    Changes since v1:
    - Rebased on tag v6.1-rc5.
    - Rewrote the clock and reset drivers using auxiliary bus framework, so
    patch 8, 9, 15 were dropped and all patches changed a lot. (by Stephen)
    - Split Patch 14 into two patches. One is for factoring out the common
    JH71X0 code, the another one is for renaming. (by Stephen)
    - Created a subdirectory for StarFive reset drivers.
    - Factored out common JH71X0 reset code.
    - Renamed the common clock and reset code from "*starfive*" or
    "*STARFIVE*" to "*jh71x0*" or "*JH71X0*".
    - Combined JH7110 system and always-on clock DT binding headers in one
    file named "include/dt-bindings/clock/starfive-jh7110.h".
    - Renamed clock definitions "JH7110_SYSCLK_PCLK2_MUX_FUNC_PCLK" and
    "JH7110_SYSCLK_U2_PCLK_MUX_PCLK" to "JH7110_SYSCLK_PCLK2_MUX_FUNC" and
    "JH7110_SYSCLK_PCLK2_MUX".
    - Rewrote the DT bindings of clock and reset for using auxiliary bus.
    - Registered an auxiliary device for reset controller in clock drivers.
    - Changed clock names "CODAJ*" and "WAVE*" to "codaj*" and "wave*".
    Changed clock names "u2_pclk_mux_func_pclk" and "u2_pclk_mux_pclk" to
    "pclk2_mux_func" and "pclk2_mux".
    - Changed the flags of clock apb0 and noc_bus_isp_axi to CLK_IS_CRITICAL
    as suggested by StarFive SDK group.
    - Registered clock gmac0_gtxc as a gate clock instead of a div clock
    as suggested by StarFive SDK group.
    - Changed the frequency of clock pll2_out to 1188MHz as suggested by
    StarFive SDK group.
    - Fixed the bug that the clock JH7110_AONCLK_GMAC0_GTXCLK was not handled
    in JH7110 always-on clock driver.
    - Registered the reset driver as an auxiliary driver.
    - Reworded the commit messages.

    v1: https://lore.kernel.org/all/20220929143225.17907-1-hal.feng@linux.starfivetech.com/

    Emil Renner Berthing (10):
    clk: starfive: Factor out common JH7100 and JH7110 code
    clk: starfive: Rename "jh7100" to "jh71x0" for the common code
    reset: Create subdirectory for StarFive drivers
    reset: starfive: Factor out common JH71X0 reset code
    reset: starfive: Rename "jh7100" to "jh71x0" for the common code
    reset: starfive: jh71x0: Use 32bit I/O on 32bit registers
    dt-bindings: clock: Add StarFive JH7110 system clock and reset
    generator
    dt-bindings: clock: Add StarFive JH7110 always-on clock and reset
    generator
    clk: starfive: Add StarFive JH7110 system clock driver
    clk: starfive: Add StarFive JH7110 always-on clock driver

    Hal Feng (1):
    reset: starfive: Add StarFive JH7110 reset driver

    .../clock/starfive,jh7110-aoncrg.yaml | 76 ++
    .../clock/starfive,jh7110-syscrg.yaml | 80 ++
    MAINTAINERS | 16 +-
    drivers/clk/starfive/Kconfig | 27 +
    drivers/clk/starfive/Makefile | 6 +-
    .../clk/starfive/clk-starfive-jh7100-audio.c | 74 +-
    drivers/clk/starfive/clk-starfive-jh7100.c | 713 +++++-------------
    drivers/clk/starfive/clk-starfive-jh7100.h | 112 ---
    .../clk/starfive/clk-starfive-jh7110-aon.c | 156 ++++
    .../clk/starfive/clk-starfive-jh7110-sys.c | 448 +++++++++++
    drivers/clk/starfive/clk-starfive-jh71x0.c | 387 ++++++++++
    drivers/clk/starfive/clk-starfive-jh71x0.h | 122 +++
    drivers/reset/Kconfig | 8 +-
    drivers/reset/Makefile | 2 +-
    drivers/reset/reset-starfive-jh7100.c | 173 -----
    drivers/reset/starfive/Kconfig | 20 +
    drivers/reset/starfive/Makefile | 5 +
    .../reset/starfive/reset-starfive-jh7100.c | 74 ++
    .../reset/starfive/reset-starfive-jh7110.c | 64 ++
    .../reset/starfive/reset-starfive-jh71x0.c | 129 ++++
    .../reset/starfive/reset-starfive-jh71x0.h | 20 +
    .../dt-bindings/clock/starfive,jh7110-crg.h | 225 ++++++
    .../dt-bindings/reset/starfive,jh7110-crg.h | 154 ++++
    23 files changed, 2234 insertions(+), 857 deletions(-)
    create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-aoncrg.yaml
    create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
    delete mode 100644 drivers/clk/starfive/clk-starfive-jh7100.h
    create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-aon.c
    create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c
    create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.c
    create mode 100644 drivers/clk/starfive/clk-starfive-jh71x0.h
    delete mode 100644 drivers/reset/reset-starfive-jh7100.c
    create mode 100644 drivers/reset/starfive/Kconfig
    create mode 100644 drivers/reset/starfive/Makefile
    create mode 100644 drivers/reset/starfive/reset-starfive-jh7100.c
    create mode 100644 drivers/reset/starfive/reset-starfive-jh7110.c
    create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.c
    create mode 100644 drivers/reset/starfive/reset-starfive-jh71x0.h
    create mode 100644 include/dt-bindings/clock/starfive,jh7110-crg.h
    create mode 100644 include/dt-bindings/reset/starfive,jh7110-crg.h


    base-commit: 830b3c68c1fb1e9176028d02ef86f3cf76aa2476
    --
    2.38.1

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