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    SubjectRe: [PATCH v5 6/6] soc: renesas: Add L2 cache management for RZ/Five SoC
    Hi Geert,

    On Thu, Dec 15, 2022 at 11:10 AM Geert Uytterhoeven
    <geert@linux-m68k.org> wrote:
    >
    > Hi Prabhakar,
    >
    > On Thu, Dec 15, 2022 at 12:06 PM Lad, Prabhakar
    > <prabhakar.csengg@gmail.com> wrote:
    > > On Thu, Dec 15, 2022 at 10:36 AM Geert Uytterhoeven
    > > <geert@linux-m68k.org> wrote:
    > > > On Mon, Dec 12, 2022 at 12:58 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
    > > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    > > > >
    > > > > I/O Coherence Port (IOCP) provides an AXI interface for connecting
    > > > > external non-caching masters, such as DMA controllers. The accesses
    > > > > from IOCP are coherent with D-Caches and L2 Cache.
    > > > >
    > > > > IOCP is a specification option and is disabled on the Renesas RZ/Five
    > > > > SoC due to this reason IP blocks using DMA will fail.
    > > > >
    > > > > The Andes AX45MP core has a Programmable Physical Memory Attributes (PMA)
    > > > > block that allows dynamic adjustment of memory attributes in the runtime.
    > > > > It contains a configurable amount of PMA entries implemented as CSR
    > > > > registers to control the attributes of memory locations in interest.
    > > > > Below are the memory attributes supported:
    > > > > * Device, Non-bufferable
    > > > > * Device, bufferable
    > > > > * Memory, Non-cacheable, Non-bufferable
    > > > > * Memory, Non-cacheable, Bufferable
    > > > > * Memory, Write-back, No-allocate
    > > > > * Memory, Write-back, Read-allocate
    > > > > * Memory, Write-back, Write-allocate
    > > > > * Memory, Write-back, Read and Write-allocate
    > > > >
    > > > > More info about PMA (section 10.3):
    > > > > Link: http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
    > > > >
    > > > > As a workaround for SoCs with IOCP disabled CMO needs to be handled by
    > > > > software. Firstly OpenSBI configures the memory region as
    > > > > "Memory, Non-cacheable, Bufferable" and passes this region as a global
    > > > > shared dma pool as a DT node. With DMA_GLOBAL_POOL enabled all DMA
    > > > > allocations happen from this region and synchronization callbacks are
    > > > > implemented to synchronize when doing DMA transactions.
    > > > >
    > > > > Example PMA region passes as a DT node from OpenSBI:
    > > > > reserved-memory {
    > > > > #address-cells = <2>;
    > > > > #size-cells = <2>;
    > > > > ranges;
    > > > >
    > > > > pma_resv0@58000000 {
    > > > > compatible = "shared-dma-pool";
    > > > > reg = <0x0 0x58000000 0x0 0x08000000>;
    > > > > no-map;
    > > > > linux,dma-default;
    > > > > };
    > > > > };
    > > > >
    > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
    > > >
    > > > Thanks for your patch!
    > > >
    > > > > arch/riscv/include/asm/cacheflush.h | 8 +
    > > > > arch/riscv/include/asm/errata_list.h | 28 ++-
    > > > > drivers/soc/renesas/Kconfig | 6 +
    > > > > drivers/soc/renesas/Makefile | 2 +
    > > > > drivers/soc/renesas/rzfive/Kconfig | 6 +
    > > > > drivers/soc/renesas/rzfive/Makefile | 3 +
    > > > > drivers/soc/renesas/rzfive/ax45mp_cache.c | 256 ++++++++++++++++++++++
    > > >
    > > > Given this touches arch/riscv/include/asm/, I don't think the
    > > > code belongs under drivers/soc/renesas/.
    > > >
    > > Ok. Do you have any suggestions on where you want me to put this code?
    >
    > As it plugs into core riscv functionality, I think it should be under
    > arch/riscv/.
    > if the RISC-V maintainers object to that, another option is
    > drivers/soc/andestech/ or (new) drivers/cache/
    >
    RISC-V maintainers had already made it clear to not to include vendor
    specific stuff in the arch/riscv folder, so I'll consider putting this
    into drivers/cache/ folder to sync with the bindings.

    Conor/Palmer - do you have any objections/suggestions?

    Cheers,
    Prabhakar

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