Messages in this thread | ![/](/images/icornerl.gif) | | Date | Wed, 14 Dec 2022 09:19:12 -0500 | From | Brian Masney <> | Subject | Re: [PATCH 3/4] arm64: dts: qcom: sa8540p-ride: add qup1_i2c15 and qup2_i2c18 nodes |
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On Wed, Dec 14, 2022 at 01:52:17PM +0100, Krzysztof Kozlowski wrote: > On 14/12/2022 13:30, Brian Masney wrote: > > I triple checked that I have the QUP pins defined correctly for the 5 > > buses. I checked them against what's in the downstream kernel and I also > > checked them against what's in upstream's > > drivers/pinctrl/qcom/pinctrl-sc8280xp.c. This is the pin mapping that I > > What's the base of this kernel? Are you sure you have d21f4b7ffc22?
I'm based on top of linux-next-20221208 with no other changes. I have that commit.
commit d21f4b7ffc22c009da925046b69b15af08de9d75 Author: Douglas Anderson <dianders@chromium.org> Date: Fri Oct 14 10:33:18 2022 -0700
pinctrl: qcom: Avoid glitching lines when we first mux to output
On Wed, Dec 14, 2022 at 01:53:38PM +0100, Konrad Dybcio wrote: > > This is the style where i2cdetect seems to be happy for all 5 buses and > > is fast: > > > > i2c0_default: i2c0-default-state { > > mux-pins { > > pins = "gpio135", "gpio136"; > > function = "qup0"; > > }; > > > > config-pins { > > pins = "gpio135", "gpio136"; > > drive-strength = <2>; > > bias-pull-up; > > }; > > }; > Unless you made a typo somewhere, I genuinely have no explanation for this..
I have my unpublished v2 patch set committed to my tree and a clean tree according to git. I started with the state that I have quoted above. As I did the various tests I described in my last email, I would do a 'git diff' just to be sure that I didn't have any typos.
I'll wait to hear from Shazad about whether or not the output that I got from i2cdetect is supposed to be the same for those 5 buses.
Brian
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