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    SubjectRe: [PATCH v10 098/108] KVM: TDX: Implement callbacks for MSR operations for TDX
    Date
    On Sat, 2022-10-29 at 23:23 -0700, isaku.yamahata@intel.com wrote:
    > +bool tdx_is_emulated_msr(u32 index, bool write)
    > +{
    > + switch (index) {
    > + case MSR_IA32_UCODE_REV:
    > + case MSR_IA32_ARCH_CAPABILITIES:
    > + case MSR_IA32_POWER_CTL:
    > + case MSR_MTRRcap:
    > + case 0x200 ... 0x26f:
    > + /* IA32_MTRR_PHYS{BASE, MASK}, IA32_MTRR_FIX*_* */
    > + case MSR_IA32_CR_PAT:
    > + case MSR_MTRRdefType:
    > + case MSR_IA32_TSC_DEADLINE:
    > + case MSR_IA32_MISC_ENABLE:
    > + case MSR_KVM_STEAL_TIME:
    > + case MSR_KVM_POLL_CONTROL:

    To me putting KVM para-virt MSRs and hardware MSRs together isn't good idea.
    You can introduce separate helpers for them.

    > + case MSR_PLATFORM_INFO:
    > + case MSR_MISC_FEATURES_ENABLES:
    > + case MSR_IA32_MCG_CAP:
    > + case MSR_IA32_MCG_STATUS:
    > + case MSR_IA32_MCG_CTL:
    > + case MSR_IA32_MCG_EXT_CTL:
    > + case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
    > + case MSR_IA32_MC0_CTL2 ... MSR_IA32_MCx_CTL2(KVM_MAX_MCE_BANKS) - 1:
    > + /* MSR_IA32_MCx_{CTL, STATUS, ADDR, MISC, CTL2} */
    > + return true;
    > + case APIC_BASE_MSR ... APIC_BASE_MSR + 0xff:
    > + /*
    > + * x2APIC registers that are virtualized by the CPU can't be
    > + * emulated, KVM doesn't have access to the virtual APIC page.
    > + */
    > + switch (index) {
    > + case X2APIC_MSR(APIC_TASKPRI):
    > + case X2APIC_MSR(APIC_PROCPRI):
    > + case X2APIC_MSR(APIC_EOI):
    > + case X2APIC_MSR(APIC_ISR) ... X2APIC_MSR(APIC_ISR + APIC_ISR_NR):
    > + case X2APIC_MSR(APIC_TMR) ... X2APIC_MSR(APIC_TMR + APIC_ISR_NR):
    > + case X2APIC_MSR(APIC_IRR) ... X2APIC_MSR(APIC_IRR + APIC_ISR_NR):
    > + return false;
    > + default:
    > + return true;
    > + }
    > + case MSR_IA32_APICBASE:
    > + case MSR_EFER:
    > + return !write;
    > + default:
    > + return false;
    > + }
    > +}

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