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    Subject[PATCH V6 16/24] mmc: sdhci-uhs2: add clock operations
    Date
    This is a sdhci version of mmc's uhs2_[enable|disable]_clk operations.

    Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
    Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
    Signed-off-by: Victor Shih <victor.shih@genesyslogic.com.tw>
    ---
    drivers/mmc/host/sdhci-uhs2.c | 32 ++++++++++++++++++++++++++++++++
    1 file changed, 32 insertions(+)

    diff --git a/drivers/mmc/host/sdhci-uhs2.c b/drivers/mmc/host/sdhci-uhs2.c
    index 52587025d5e3..c7e411fa0a6e 100644
    --- a/drivers/mmc/host/sdhci-uhs2.c
    +++ b/drivers/mmc/host/sdhci-uhs2.c
    @@ -14,6 +14,7 @@
    #include <linux/module.h>
    #include <linux/iopoll.h>
    #include <linux/bitfield.h>
    +#include <linux/ktime.h>

    #include "sdhci.h"
    #include "sdhci-uhs2.h"
    @@ -329,6 +330,37 @@ int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
    return 0;
    }

    +static int sdhci_uhs2_disable_clk(struct mmc_host *mmc)
    +{
    + struct sdhci_host *host = mmc_priv(mmc);
    + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
    +
    + clk &= ~SDHCI_CLOCK_CARD_EN;
    + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
    +
    + return 0;
    +}
    +
    +static int sdhci_uhs2_enable_clk(struct mmc_host *mmc)
    +{
    + struct sdhci_host *host = mmc_priv(mmc);
    + u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
    + u32 val;
    + /* 20ms */
    + int timeout_us = 20000;
    +
    + clk |= SDHCI_CLOCK_CARD_EN;
    + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
    +
    + if (read_poll_timeout_atomic(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE),
    + 10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) {
    + pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc));
    + sdhci_dumpregs(host);
    + return 1;
    + }
    + return 0;
    +}
    +
    /*****************************************************************************\
    * *
    * Driver init/exit *
    --
    2.25.1
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