Messages in this thread | | | From | Geert Uytterhoeven <> | Date | Thu, 1 Dec 2022 10:34:25 +0100 | Subject | Re: [PATCH v2 3/7] clk: renesas: r8a779g0: Add display related clocks |
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Hi Tomi,
On Thu, Dec 1, 2022 at 10:06 AM Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> wrote: > On 30/11/2022 21:18, Geert Uytterhoeven wrote: > > On Wed, Nov 23, 2022 at 8:00 AM Tomi Valkeinen > > <tomi.valkeinen+renesas@ideasonboard.com> wrote: > >> Add clocks related to display which are needed to get the DSI output > >> working. > >> > >> Extracted from Renesas BSP tree. > >> > >> Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> > >> Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com> > >> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Not that all of this matters a lot: all of these parents are always-on, > > and I think "dis0" is the only clock where we care about the actual > > clock rate? > > No, of the clocks added above, in the drivers we only care about the > dsiref rate. That's used for the DSI PLL, and that PLL is used as the > DU's pclk.
IC. As the DU node has only a single clocks property, I thought that clock is used to derive the pixel clock from.
Gr{oetje,eeting}s,
Geert
-- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds
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