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    Subject[PATCH v4 3/7] soc: amlogic: meson-pwrc: Add NNA power domain for A311D
    Date
    Based on power initialization sequence in downstream driver.

    Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
    Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
    ---
    drivers/soc/amlogic/meson-ee-pwrc.c | 17 +++++++++++++++++
    1 file changed, 17 insertions(+)

    diff --git a/drivers/soc/amlogic/meson-ee-pwrc.c b/drivers/soc/amlogic/meson-ee-pwrc.c
    index dd5f2a13ceb5..dfbf0b1c7d29 100644
    --- a/drivers/soc/amlogic/meson-ee-pwrc.c
    +++ b/drivers/soc/amlogic/meson-ee-pwrc.c
    @@ -46,6 +46,9 @@
    #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
    #define HHI_VPU_MEM_PD_REG2 (0x4d << 2)

    +#define G12A_HHI_NANOQ_MEM_PD_REG0 (0x43 << 2)
    +#define G12A_HHI_NANOQ_MEM_PD_REG1 (0x44 << 2)
    +
    struct meson_ee_pwrc;
    struct meson_ee_pwrc_domain;

    @@ -106,6 +109,13 @@ static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
    static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
    static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);

    +static struct meson_ee_pwrc_top_domain g12a_pwrc_nna = { \
    + .sleep_reg = GX_AO_RTI_GEN_PWR_SLEEP0, \
    + .sleep_mask = BIT(16) | BIT(17), \
    + .iso_reg = GX_AO_RTI_GEN_PWR_ISO0, \
    + .iso_mask = BIT(16) | BIT(17), \
    + };
    +
    /* Memory PD Domains */

    #define VPU_MEMPD(__reg) \
    @@ -217,6 +227,11 @@ static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
    { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
    };

    +static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_nna[] = {
    + { G12A_HHI_NANOQ_MEM_PD_REG0, GENMASK(31, 0) },
    + { G12A_HHI_NANOQ_MEM_PD_REG1, GENMASK(23, 0) },
    +};
    +
    #define VPU_PD(__name, __top_pd, __mem, __is_pwr_off, __resets, __clks) \
    { \
    .name = __name, \
    @@ -253,6 +268,8 @@ static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
    [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &gx_pwrc_vpu, g12a_pwrc_mem_vpu,
    pwrc_ee_is_powered_off, 11, 2),
    [PWRC_G12A_ETH_ID] = MEM_PD("ETH", meson_pwrc_mem_eth),
    + [PWRC_G12A_NNA_ID] = TOP_PD("NNA", &g12a_pwrc_nna, g12a_pwrc_mem_nna,
    + pwrc_ee_is_powered_off),
    };

    static struct meson_ee_pwrc_domain_desc gxbb_pwrc_domains[] = {
    --
    2.38.1
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