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    SubjectRe: [PATCH v3 1/9] cxl/acpi: Register CXL host ports by bridge device
    On Wed, Nov 09, 2022 at 11:40:51AM +0100, Robert Richter wrote:
    > A port of a CXL host bridge links to the bridge's acpi device

    s/acpi/ACPI/ to match usage below.

    > (&adev->dev) with its corresponding uport/dport device (uport_dev and
    > dport_dev respectively). The device is not a direct parent device in
    > the PCI topology as pdev->dev.parent points to a PCI bridge's (struct
    > pci_host_bridge) device. The following CXL memory device hierarchy
    > would be valid for an endpoint once an RCD EP would be enabled (note
    > this will be done in a later patch):
    >
    > VH mode:
    >
    > cxlmd->dev.parent->parent
    > ^^^\^^^^^^\ ^^^^^^\
    > \ \ pci_dev (Type 1, Downstream Port)
    > \ pci_dev (Type 0, PCI Express Endpoint)
    > cxl mem device
    >
    > RCD mode:
    >
    > cxlmd->dev.parent->parent
    > ^^^\^^^^^^\ ^^^^^^\
    > \ \ pci_host_bridge
    > \ pci_dev (Type 0, RCiEP)
    > cxl mem device
    >
    > In VH mode a downstream port is created by port enumeration and thus
    > always exists.
    >
    > Now, in RCD mode the host bridge also already exists but it references
    > to an ACPI device. A port lookup by the PCI device's parent device
    > will fail as a direct link to the registered port is missing. The ACPI
    > device of the bridge must be determined first.
    >
    > To prevent this, change port registration of a CXL host to use the
    > bridge device instead. Do this also for the VH case as port topology
    > will better reflect the PCI topology then.
    >
    > If a mock device is registered by a test driver, the bridge pointer
    > can be NULL. Keep using the matching ACPI device (&adev->dev) as a
    > fallback in this case.
    >
    > Signed-off-by: Robert Richter <rrichter@amd.com>

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