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    SubjectRe: [PATCH v3 6/9] cxl/pci: Do not ignore PCI config read errors in match_add_dports()
    On Wed, Nov 09, 2022 at 11:40:56AM +0100, Robert Richter wrote:
    > The link capabilities of a PCI device are read when enumerating its
    > dports. This is done by reading the PCI config space. If that fails
    > port enumeration ignores that error. However, reading the PCI config
    > space should reliably work.
    >
    > To reduce some complexity to the code flow when factoring out parts of
    > the code in match_add_dports() for later reuse, change this to throw
    > an error.
    >
    > Signed-off-by: Robert Richter <rrichter@amd.com>
    > ---
    > drivers/cxl/core/pci.c | 2 +-
    > 1 file changed, 1 insertion(+), 1 deletion(-)
    >
    > diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
    > index 0dbbe8d39b07..8271b8abde7a 100644
    > --- a/drivers/cxl/core/pci.c
    > +++ b/drivers/cxl/core/pci.c
    > @@ -47,7 +47,7 @@ static int match_add_dports(struct pci_dev *pdev, void *data)
    > return 0;
    > if (pci_read_config_dword(pdev, pci_pcie_cap(pdev) + PCI_EXP_LNKCAP,
    > &lnkcap))

    You didn't change this, but I recommend using
    pcie_capability_read_dword() when reading the PCIe Capability. It
    takes care of some annoying corner cases like devices that don't
    implement Link Cap and the different versions of the PCIe Capability.

    > - return 0;
    > + return -ENXIO;
    >
    > rc = cxl_find_regblock(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
    > if (rc)
    > --
    > 2.30.2
    >

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