Messages in this thread | | | From | Ard Biesheuvel <> | Date | Mon, 7 Nov 2022 13:02:00 +0100 | Subject | Re: [PATCH V2] arm64/mm: Simplify and document pte_to_phys() for 52 bit addresses |
| |
Hello Anshuman,
On Mon, 7 Nov 2022 at 12:49, Anshuman Khandual <anshuman.khandual@arm.com> wrote: > > pte_to_phys() assembly definition does multiple bits field transformations > to derive physical address, embedded inside a page table entry. Unlike its > C counter part i.e __pte_to_phys(), pte_to_phys() is not very apparent. It > simplifies these operations via a new macro PTE_ADDR_HIGH_SHIFT indicating > how far the pte encoded higher address bits need to be left shifted. While > here, this also updates __pte_to_phys() and __phys_to_pte_val(). > > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > Cc: Mark Brown <broonie@kernel.org> > Cc: Mark Rutland <mark.rutland@arm.com> > Cc: Ard Biesheuvel <ardb@kernel.org> > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Suggested-by: Ard Biesheuvel <ardb@kernel.org> > Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
With the nit below fixed, this looks good to me
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
> --- > This applies on v6.1-rc4 > > Changes in V2: > > - Added PTE_ADDR_HIGH_SHIFT based method per Ard > > Changes in V1: > > https://lore.kernel.org/all/20221031082421.1957288-1-anshuman.khandual@arm.com/ > > arch/arm64/include/asm/assembler.h | 8 +++----- > arch/arm64/include/asm/pgtable-hwdef.h | 1 + > arch/arm64/include/asm/pgtable.h | 4 ++-- > 3 files changed, 6 insertions(+), 7 deletions(-) > > diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h > index e5957a53be39..6a39a3601cf7 100644 > --- a/arch/arm64/include/asm/assembler.h > +++ b/arch/arm64/include/asm/assembler.h > @@ -660,12 +660,10 @@ alternative_endif > .endm > > .macro pte_to_phys, phys, pte > -#ifdef CONFIG_ARM64_PA_BITS_52 > - ubfiz \phys, \pte, #(48 - 16 - 12), #16 > - bfxil \phys, \pte, #16, #32 > - lsl \phys, \phys, #16 > -#else > and \phys, \pte, #PTE_ADDR_MASK > +#ifdef CONFIG_ARM64_PA_BITS_52 > + orr \phys, \phys, \phys, lsl #PTE_ADDR_HIGH_SHIFT > + and \phys, \phys, GENMASK_ULL(PHYS_MASK_SHIFT - 1, PAGE_SHIFT)
Please use tabs between the mnemonics and the arguments.
> #endif > .endm > > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h > index 5ab8d163198f..f658aafc47df 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -159,6 +159,7 @@ > #ifdef CONFIG_ARM64_PA_BITS_52 > #define PTE_ADDR_HIGH (_AT(pteval_t, 0xf) << 12) > #define PTE_ADDR_MASK (PTE_ADDR_LOW | PTE_ADDR_HIGH) > +#define PTE_ADDR_HIGH_SHIFT 36 > #else > #define PTE_ADDR_MASK PTE_ADDR_LOW > #endif > diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h > index 71a1af42f0e8..daedd6172227 100644 > --- a/arch/arm64/include/asm/pgtable.h > +++ b/arch/arm64/include/asm/pgtable.h > @@ -77,11 +77,11 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)]; > static inline phys_addr_t __pte_to_phys(pte_t pte) > { > return (pte_val(pte) & PTE_ADDR_LOW) | > - ((pte_val(pte) & PTE_ADDR_HIGH) << 36); > + ((pte_val(pte) & PTE_ADDR_HIGH) << PTE_ADDR_HIGH_SHIFT); > } > static inline pteval_t __phys_to_pte_val(phys_addr_t phys) > { > - return (phys | (phys >> 36)) & PTE_ADDR_MASK; > + return (phys | (phys >> PTE_ADDR_HIGH_SHIFT)) & PTE_ADDR_MASK; > } > #else > #define __pte_to_phys(pte) (pte_val(pte) & PTE_ADDR_MASK) > -- > 2.25.1 >
| |