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    Subject[PATCH V3 04/14] arm64: dts: imx8mp-evk: enable uart1/3 ports
    Date
    From: Peng Fan <peng.fan@nxp.com>

    Enable uart1/3 ports for evk board.
    Configure the clock to source from IMX8MP_SYS_PLL1_80M, because the uart
    could only support max 1.5M buadrate if using OSC_24M as clock source.

    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    Reviewed-by: Marco Felsch <m.felsch@pengutronix.de>
    ---
    arch/arm64/boot/dts/freescale/imx8mp-evk.dts | 36 ++++++++++++++++++++
    1 file changed, 36 insertions(+)

    diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
    index e323e6f4b7e5..29472502d547 100644
    --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
    +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts
    @@ -412,6 +412,15 @@ &snvs_pwrkey {
    status = "okay";
    };

    +&uart1 { /* BT */
    + pinctrl-names = "default";
    + pinctrl-0 = <&pinctrl_uart1>;
    + assigned-clocks = <&clk IMX8MP_CLK_UART1>;
    + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
    + fsl,uart-has-rtscts;
    + status = "okay";
    +};
    +
    &uart2 {
    /* console */
    pinctrl-names = "default";
    @@ -434,6 +443,15 @@ &usb_dwc3_1 {
    status = "okay";
    };

    +&uart3 {
    + pinctrl-names = "default";
    + pinctrl-0 = <&pinctrl_uart3>;
    + assigned-clocks = <&clk IMX8MP_CLK_UART3>;
    + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>;
    + fsl,uart-has-rtscts;
    + status = "okay";
    +};
    +
    &usdhc2 {
    assigned-clocks = <&clk IMX8MP_CLK_USDHC2>;
    assigned-clock-rates = <400000000>;
    @@ -609,6 +627,15 @@ MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
    >;
    };

    + pinctrl_uart1: uart1grp {
    + fsl,pins = <
    + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140
    + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140
    + MX8MP_IOMUXC_UART3_RXD__UART1_DCE_CTS 0x140
    + MX8MP_IOMUXC_UART3_TXD__UART1_DCE_RTS 0x140
    + >;
    + };
    +
    pinctrl_uart2: uart2grp {
    fsl,pins = <
    MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
    @@ -622,6 +649,15 @@ MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
    >;
    };

    + pinctrl_uart3: uart3grp {
    + fsl,pins = <
    + MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x140
    + MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX 0x140
    + MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS 0x140
    + MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS 0x140
    + >;
    + };
    +
    pinctrl_usdhc2: usdhc2grp {
    fsl,pins = <
    MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190
    --
    2.37.1
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