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    Subject[PATCH v6 12/20] dt-bindings: PCI: dwc: Add dma-coherent property
    Date
    DW PCIe EP/RP AXI- and TRGT1-master interfaces are responsible for the
    application memory access. They are used by the RP/EP PCIe buses (MWr/MWr
    TLPs emitted by the peripheral PCIe devices) and the eDMA block. Since all
    of them mainly involve the system memory and basically mean DMA we can
    expect the corresponding platforms can be designed in a way to make sure
    the transactions are cache-coherent. As such the DW PCIe DT-nodes can have
    the 'dma-coherent' property specified. Let's permit it in the DT-bindings
    then.

    Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
    Reviewed-by: Rob Herring <robh@kernel.org>

    ---

    Changelog v3:
    - This is a new patch created on v3 lap of the series.
    ---
    Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml | 2 ++
    1 file changed, 2 insertions(+)

    diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
    index 4d9efcea3859..d87e13496834 100644
    --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
    +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie-common.yaml
    @@ -259,6 +259,8 @@ properties:
    configuration space registers, Port Logic registers, DMA and iATU
    registers. This feature has been available since DWC PCIe v4.80a.

    + dma-coherent: true
    +
    additionalProperties: true

    ...
    --
    2.38.0

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