Messages in this thread | | | Date | Mon, 7 Nov 2022 19:34:49 +0100 | Subject | Re: [PATCH v3 3/3] KVM: x86/pmu: Limit the maximum number of supported AMD GP counters | From | Paolo Bonzini <> |
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On 9/19/22 11:10, Like Xu wrote: > @@ -506,6 +506,7 @@ struct kvm_pmc { > #define MSR_ARCH_PERFMON_PERFCTR_MAX (MSR_ARCH_PERFMON_PERFCTR0 + KVM_INTEL_PMC_MAX_GENERIC - 1) > #define MSR_ARCH_PERFMON_EVENTSEL_MAX (MSR_ARCH_PERFMON_EVENTSEL0 + KVM_INTEL_PMC_MAX_GENERIC - 1) > #define KVM_PMC_MAX_FIXED 3 > +#define KVM_AMD_PMC_MAX_GENERIC AMD64_NUM_COUNTERS_CORE > struct kvm_pmu {
Even though the BUILD_BUG_ON prevents out-of-bounds accesses, this should be hardcoded to 6 to avoid mismatches with msrs_to_save_all[].
> + BUILD_BUG_ON(AMD64_NUM_COUNTERS_CORE > KVM_AMD_PMC_MAX_GENERIC);
This should be KVM_AMD_PMC_MAX_GENERIC > AMD64_NUM_COUNTERS_CORE, not the opposite.
Fixed up and changed the commit message to follow:
The AMD PerfMonV2 specification allows for a maximum of 16 GP counters, but currently only 6 pairs of MSRs are accepted by KVM.
While AMD64_NUM_COUNTERS_CORE is already equal to 6, increasing without adjusting msrs_to_save_all[] could result in out-of-bounds accesses. Therefore introduce a macro (named KVM_AMD_PMC_MAX_GENERIC) to refer to the number of counters supported by KVM.
Paolo
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