Messages in this thread | | | From | Anup Patel <> | Date | Wed, 30 Nov 2022 22:33:05 +0530 | Subject | Re: [PATCH v13 3/7] genirq: Add mechanism to multiplex a single HW IPI |
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On Wed, Nov 30, 2022 at 8:17 PM Marc Zyngier <maz@kernel.org> wrote: > > On Tue, 29 Nov 2022 14:24:45 +0000, > Anup Patel <apatel@ventanamicro.com> wrote: > > > > All RISC-V platforms have a single HW IPI provided by the INTC local > > interrupt controller. The HW method to trigger INTC IPI can be through > > external irqchip (e.g. RISC-V AIA), through platform specific device > > (e.g. SiFive CLINT timer), or through firmware (e.g. SBI IPI call). > > > > To support multiple IPIs on RISC-V, we add a generic IPI multiplexing > > mechanism which help us create multiple virtual IPIs using a single > > HW IPI. This generic IPI multiplexing is inspired from the Apple AIC > > irqchip driver and it is shared by various RISC-V irqchip drivers. > > > > Signed-off-by: Anup Patel <apatel@ventanamicro.com> > > --- > > include/linux/irq.h | 3 + > > kernel/irq/Kconfig | 5 ++ > > kernel/irq/Makefile | 1 + > > kernel/irq/ipi-mux.c | 193 +++++++++++++++++++++++++++++++++++++++++++ > > 4 files changed, 202 insertions(+) > > create mode 100644 kernel/irq/ipi-mux.c > > [...] > > This is finally starting to look acceptable. My only changes are: > > diff --git a/kernel/irq/ipi-mux.c b/kernel/irq/ipi-mux.c > index 626c564233e9..1a6ba19b736c 100644 > --- a/kernel/irq/ipi-mux.c > +++ b/kernel/irq/ipi-mux.c > @@ -69,6 +69,12 @@ static void ipi_mux_send_mask(struct irq_data *d, const struct cpumask *mask) > */ > smp_mb__after_atomic(); > > + /* > + * The flag writes must complete before the physical IPI is > + * issued to another CPU. This is implied by the control > + * dependency on the result of atomic_read() below, which is > + * itself already ordered after the vIPI flag write. > + */ > if (!(pending & ibit) && (atomic_read(&icpu->enable) & ibit)) > ipi_mux_send(cpu); > } > @@ -160,7 +166,7 @@ int ipi_mux_create(unsigned int nr_ipi, void (*mux_send)(unsigned int cpu)) > goto fail_free_cpu; > } > > - domain = irq_domain_create_simple(fwnode, nr_ipi, 0, > + domain = irq_domain_create_linear(fwnode, nr_ipi, > &ipi_mux_domain_ops, NULL); > if (!domain) { > pr_err("unable to add IPI Mux domain\n"); > > The first hunk preserve an important piece of information about how > delicate the ordering is, while the second only allocates the irqdesc > structures as needed, not upfront. > > I'll shortly go over the rest of the irqchip code and can apply the > above myself if there is nothing more to fix. > > I've also converted the AIC driver over to this[1], and nothing broke > so far... > > M. > > [1] https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=irq/ipi-mux
Thanks Marc, I will include your changes in the next patch revision.
> > -- > Without deviation from the norm, progress is not possible.
Regards, Anup
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