Messages in this thread | | | Date | Thu, 1 Dec 2022 12:02:50 +0800 | Subject | Re: [PATCH v3] iommu/vt-d: Add a fix for devices need extra dtlb flush | From | Baolu Lu <> |
| |
On 2022/11/30 14:24, Jacob Pan wrote: > QAT devices on Intel Sapphire Rapids and Emerald Rapids have a defect in > address translation service (ATS). These devices may inadvertently issue > ATS invalidation completion before posted writes initiated with > translated address that utilized translations matching the invalidation > address range, violating the invalidation completion ordering. > > This patch adds an extra device TLB invalidation for the affected devices, > it is needed to ensure no more posted writes with translated address > following the invalidation completion. Therefore, the ordering is > preserved and data-corruption is prevented. > > Device TLBs are invalidated under the following six conditions: > 1. Device driver does DMA API unmap IOVA > 2. Device driver unbind a PASID from a process, sva_unbind_device() > 3. PASID is torn down, after PASID cache is flushed. e.g. process > exit_mmap() due to crash > 4. Under SVA usage, called by mmu_notifier.invalidate_range() where > VM has to free pages that were unmapped > 5. userspace driver unmaps a DMA buffer > 6. Cache invalidation in vSVA usage (upcoming) > > For #1 and #2, device drivers are responsible for stopping DMA traffic > before unmap/unbind. For #3, iommu driver gets mmu_notifier to > invalidate TLB the same way as normal user unmap which will do an extra > invalidation. The dTLB invalidation after PASID cache flush does not > need an extra invalidation. > > Therefore, we only need to deal with #4 and #5 in this patch. #1 is also > covered by this patch due to common code path with #5. > > Tested-by: Yuzhang Luo<yuzhang.luo@intel.com> > Reviewed-by: Ashok Raj<ashok.raj@intel.com> > Reviewed-by: Kevin Tian<kevin.tian@intel.com> > Signed-off-by: Jacob Pan<jacob.jun.pan@linux.intel.com>
Queued for Joerg. Thank you!
Best regards, baolu
| |