Messages in this thread | | | Date | Mon, 28 Nov 2022 01:42:26 +0100 | From | Borislav Petkov <> | Subject | Re: [PATCH v2] x86/bugs: Explicitly clear speculative MSR bits |
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On Thu, Nov 24, 2022 at 02:46:50AM -0800, Breno Leitao wrote: > Currently x86_spec_ctrl_base is read at boot time, and speculative bits > are set if configs are enable, such as MSR[SPEC_CTRL_IBRS] is enabled if > CONFIG_CPU_IBRS_ENTRY is configured. These MSR bits are not cleared if > the mitigations are disabled. > > This is a problem when kexec-ing a kernel that has the mitigation > disabled, from a kernel that has the mitigation enabled. In this case, > the MSR bits are carried forward and not cleared at the boot of the new > kernel. This might have some performance degradation that is hard to > find. > > This problem does not happen if the machine is (hard) rebooted, because > the bit will be cleared by default. > > This patch also defines a SPEC_CTRL_MASK macro, so, we can easily track > and clear if eventually some new mitigation shows up.
Just remove that sentence - the macro's function is kinda obvious from the diff itself.
> Suggested-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com> > Signed-off-by: Breno Leitao <leitao@debian.org> > --- > arch/x86/include/asm/msr-index.h | 3 +++ > arch/x86/kernel/cpu/bugs.c | 9 ++++++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 4a2af82553e4..704f49580ee1 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -54,6 +54,9 @@ > #define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */ > #define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT) > > +#define SPEC_CTRL_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \ > + | SPEC_CTRL_RRSBA_DIS_S)
Call that SPEC_CTRL_MITIGATIONS_MASK or so to denote what it is - a mask of the SPEC_CTRL bits which the kernel toggles when controlling mitigations.
A comment above it wouldn't hurt either.
> + > #define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */ > #define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */ > > diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c > index 3e3230cccaa7..88957da1029b 100644 > --- a/arch/x86/kernel/cpu/bugs.c > +++ b/arch/x86/kernel/cpu/bugs.c > @@ -137,8 +137,15 @@ void __init check_bugs(void) > * have unknown values. AMD64_LS_CFG MSR is cached in the early AMD > * init code as it is not enumerated and depends on the family. > */ > - if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) > + if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) { > rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base); > + /* > + * Previously running software may have some controls turned ON.
"Previously running software, like kexec for example, ..."
> + * Clear them and let kernel decide which controls to use.
"Clear them and let the mitigations setup below set them based on configuration."
> + */ > + x86_spec_ctrl_base &= ~SPEC_CTRL_MASK; > + wrmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
So this WRMSR will happen on the BSP only but the SPEC_CTRL MSR is per-CPU. As is x86_spec_ctrl_current which tracks it.
So I'd say you don't need that WRMSR here - the proper value will get replicated eventually everywhere...
Thx.
-- Regards/Gruss, Boris.
https://people.kernel.org/tglx/notes-about-netiquette
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